JITX Documentation

#use-added-syntax(jitx)
defpackage stub-example :
  import core
  import jitx
  import jitx/commands

  import jsl/symbols
  import jsl/landpatterns

pcb-routing-structure single-ended :
  name = "50 Ohm single-ended"
  layer(Top) :
    trace-width = 0.5       ; mm
    clearance = 0.3         ; mm
    velocity = 0.19e12      ; mm/s
    insertion-loss = 0.008  ; db/mm @ 1GHz 
    neck-down:
      trace-width = 0.156   ; mm
      clearance = 0.1       ; mm

  layer(Bottom) :
    trace-width = 0.5       ; mm
    clearance = 0.3         ; mm
    velocity = 0.19e12      ; mm/s
    insertion-loss = 0.008  ; db/mm @ 1GHz 
    neck-down:
      trace-width = 0.156   ; mm
      clearance = 0.1       ; mm

pcb-component resistor-model :
  pin-properties :
    [ pin : Ref | pads : Int ... | side:Dir ]
    [ p[1]      | 1              | Left ]
    [ p[2]      | 2              | Right ]

  val symb = ResistorSymbol()
  assign-symbol $ create-symbol(symb)

  val pkg = get-chip-pkg("0603")
  assign-landpattern $ create-landpattern(pkg)

  pin-model(self.p[1]) = PinModel(typ(1.0e-12), typ(0.0))
  pin-model(self.p[2]) = PinModel(typ(1.0e-12), typ(0.0))


pcb-module top-level :

  inst A : resistor-model
  inst B : resistor-model
  inst C : resistor-model


  net (A.p[1], B.p[1])
  topology-segment(A.p[1], B.p[1])
  structure(A.p[1] => B.p[1]) = single-ended

  net (B.p[1], C.p[1])
  topology-segment(B.p[1], C.p[1])
  structure(B.p[1] => C.p[1]) = single-ended


val board-shape = RoundedRectangle(50. * 1.618, 50.0, 3.0)

set-current-design("stub-topo-test")
set-board(ocdb/utils/defaults/default-board(ocdb/manufacturers/stackups/jlcpcb-jlc2313, board-shape))
set-rules(ocdb/manufacturers/rules/jlcpcb-rules)
set-bom-vendors([JLCPCB])
set-bom-design-quantity(100)

; Set the schematic sheet size
set-paper(ANSI-A)
set-use-layout-groups()

; Set the top level module (the module to be compile into a schematic and PCB)
set-main-module(top-level)

; View the results
view-board()