Known Issues


  • CAD imports fail. Some Altium or KiCad designs may import into JITX but then fail to compile. We are solving this issue and all CAD projects will be importable in the coming weeks. If your design fails to compile after import, the first thing to do is to look at the output of the JITX Shell. It's likely the issue has to do with geometry of 1 or more of your components. Look for lines that begin with Failed to initialize physical design state: Unrecoverable: and note the component that is listed as the culprit. Then, go back to your original design and:
    • Ensure the landpattern for that component is correct. If you correct any issues, then retry.
    • If the above fails, change the landpattern of the component to a dummy landpattern (example, a header pin or oscilloscope probe landpattern), re-import, and then generate the pattern directly in JITX.
  • UI can be non-responsive when there is significant computation dedicated to the design automation.
    • To see the status of the algorithms in VSCode, go to Output (bottom of VSCode window) and select jitx-log in the dropdown.
  • Board UI goes black. In this case, just close the window, navigate to the JITX sidebar, and click "Board".

Physical Design / Layout

  • No ratnest is shown for pin-assigned nets. User must select pins that they know can be assigned to each other and click route. export-cad() can be used to make sure that everything has been assigned and routed.
  • Vias cannot be moved once created. To deal with this, simply delete the via and create a new one in the new location.
  • Not all possible pin assignments can be found by the router. Some pins that should be assignable will not be able to be assigned. Use nets, or route to a different pad.
  • The router cannot route well around imported or user-defined traces yet. Some imported geometry from CAD can be malformed and fail the checks in the routing algorithms.
  • Altium DRC errors occur after exporting from JITX.
    1. Ensure you're on the latest JITX VSCode extension version, then retry.
    2. Some errors related to disconnected vias and board edge clearance may still be thrown. These can be safely ignored. We're currently working to solve these errors.


  • Schematic changes may become slow in large schematic groups containing many symbols and pins. Create smaller groups to improve performance.
  • Your schematic might initially look like a blank screen like below. Be sure to zoom in to the bottom left corner to see the design.

    JITX Project Compiled