In this tutorial you will learn how to create a standard land pattern parameterized by the design rules and design variables within JITX.
Say we have a 20 pin thin shrink small outline package (TSSOP). The data sheet will look something like this:
Within OCDB we can use the
make-n-pin-soic-landpattern function to represent this component.
#use-added-syntax(jitx) defpackage tssop20: import core import collections import jitx import jitx/commands import ocdb/utils/landpatterns public pcb-landpattern TSSOP20 : make-n-pin-soic-landpattern( 20 ; number of pins 0.650 ; pitch, e in the table min-typ-max(6.20, 6.40, 6.60) ; lead-span, E in the table min-typ-max(4.30, 4.40, 4.50) ; package-length, E1 in the table min-typ-max(6.40, 6.50, 6.60) ; package-width, D in the table min-typ-max(0.45, 0.60, 0.75) ; lead length, L in the table min-typ-max(1.9, (3.0 + 1.9) / 2.0, 3.0) ; lead width, b in the table )
Now we can use this in a component.
#use-added-syntax(jitx) defpackage STM32F031x4 : import core import collections import jitx import jitx/commands import ocdb/utils/box-symbol import tssop20 public pcb-component component : name: "STM32F031x4" pin-properties : [pin: Ref | pads: Int ... | side: Dir] [BOOT | 1 | Left ] [OSC_IN | 2 | Left ] [OSC_OUT | 3 | Left ] [NRST | 4 | Left ] [VDDA | 5 | Left ] [PA | 6 | Left ] [PA | 7 | Left ] [PA | 8 | Left ] [PA | 9 | Left ] [PA | 10 | Left ] [PA | 11 | Right ] [PA | 12 | Right ] [PA | 13 | Right ] [PB | 14 | Right ] [VSS | 15 | Right ] [VDD | 16 | Right ] [PA | 17 | Right ] [PA | 18 | Right ] [PA | 19 | Right ] [PA | 20 | Right ] assign-landpattern(TSSOP20) make-box-symbol()
Now that we have a component with a land pattern and symbol we can place it in a design
defpackage my-design : import core import collections import jitx import ocdb/utils/box-symbol import jitx/commands import ocdb/utils/defaults import ocdb/utils/design-vars import ocdb/manufacturers/rules import stm32F031x4 pcb-module my-design : inst mcu : stm32F031x4/component place(mcu) at loc(0.0, 0.0) on Top make-default-board(my-design, 4, Rectangle(10.0, 10.0)) view-board()
The visualizer shows us our generated component.
Under the hood the land pattern is parameterized by your design variables and design rules. We can see how the generated land pattern is altered when we change our design rules.
For example: in the previous screen shot the solder mask bridging may present an issue during manufacturing. We can choose a more precise manufacturing process for this design, and represent that by setting the corresponding design rules.
set-rules(sierra-circuits-notouch-rules) make-default-board(my-design, 4, Rectangle(10.0, 10.0)) view-board()
The generated land pattern now appears to have wider solder mask bridges, due to the fact the design process has a tighter solder mask registration which is covered by the design rules.
You may also notice that the courtyard for this component is very tight - this is because the density level of our design is the highest by default. We can choose a less dense design, to contrast we'll use the least dense level,
DENSITY-LEVEL = LevelB set-rules(sierra-circuits-notouch-rules) make-default-board(my-design, 4, Rectangle(10.0, 10.0)) view-board()
Our generated land pattern now has a larger courtyard, and the heel/toe/sides of the pads has grown slightly as well.
Density levels and other design variables are documented here
There are many more land pattern generators, see the documentation for details.