timing-difference

The timing-difference statement is a means of applying a timing skew constraint between two signal topologies. A typical application is "length matching" the P/N signals of a differential pair. This constraint is used by the routing engine to apply the appropriate skew matching routes (lovingly referred to as "squiggles").

The skew between two signal topologies is formulated as a time difference instead of a length difference because different layers, routing structures, and layers may have different propagation delays associated with them.

This statement is only valid within the pcb-module context.

This constraints are applied to the endpoints of a signal topology. The routing engine will infer that this constraint must be applied to every segment of the topology between the passed endpoints.

Signature

timing-difference(<EXP-1>, <EXP-2>) = <TimingDifferenceConstraint>

The timing-difference statement expects two expressions that outline the endpoints of two signal topologies. Each of these expressions is expected to be a KeyValue representing the two endpoints of each signal topology.

The simplest form of this statement looks something like this:

timing-difference( <REF-A-1> => <REF-A-2>, <REF-B-1> => <REF-B-2>) = <TimingDifferenceConstraint>

Here each of the <REF-*-*> are refs to SinglePin port of a component, module, or abstract (require) port.

In most applications, the endpoints are the extrema of a signal topology.

Constructing cycles in these constraints is disallowed. This means that <REF-A-1> cannot be the same port as <REF-A-2>.

TimingDifferenceConstraint

An instance of TimingDifferenceConstraint is applied to the timing-difference statement:

defstruct TimingDifferenceConstraint <: SignalConstraint :
  min-delta:Double
  max-delta:Double

defn TimingDifferenceConstraint (delta: Toleranced) :
  ...

The min-delta and max-delta are relative skew limits in units of seconds between the two signal routes to be constrained. max-delta must be greater than min-delta.

It is typical in most applications for min-delta to be negative and max-delta to be positive.

The delay introduced by a particular signal route is determined by the Routing Structure applied via the structure statement.

Usage

The most common application is for intra differential pair skew, but this can also be used to apply interpair or bus skew constraints:

pcb-differential-routing-structure diff-100:
  name = "100 Ohm Diff Impedance"
  ...

pcb-bundle MIPI-CSI (lane-cnt:Int): 
  port clk : diff-pair
  port data : diff-pair[lane-cnt]

pcb-component CMOSImageArray : 
  port mipi : MIPI-CSI(1)
  ...

pcb-component MCU : 
  port mipi : MIPI-CSI(1)

pcb-module camera: 

  inst mcu : MCU
  inst imager : CMOSImageArray

  topo-net(mcu.mipi => imager.mipi)

  structure(mcu.mipi.clk => imager.mipi.clk) = diff-100
  for i in 0 to length(mcu.mipi.data) do:
    structure(mcu.mipi.data[i] => imager.mipi.data[i]) = diff-100

  ; Intra-Pair Skew - P / N
  val intra-skew = TimingDifferenceConstraint(0.0 +/- 10.0e-12)

  timing-difference(
    mcu.mipi.clk.P => imager.mipi.clk.P,
    mcu.mipi.clk.N => imager.mipi.clk.N,
  ) = intra-skew

  for i in 0 to length(mcu.mipi.data) do:
    timing-difference(
      mcu.mipi.data[i].P => imager.mipi.data[i].P,
      mcu.mipi.data[i].N => imager.mipi.data[i].N,
    ) = intra-skew

  ; Inter Pair Skew - Clk to Data

  val inter-skew = TimingDifferenceConstraint(0.0 +/- 25.0e-12)

  timing-difference(
    mcu.mipi.clk.P => mcu.mipi.clk.P,
    mcu.mipi.data[0].P => mcu.mipi.data[0].P
  ) = inter-skew

In this example, we introduce both a intra-pair skew constraint for each of the differential pairs of the MIPI interface, as well as a inter-pair skew constraint between the clock and data differential pairs.

Notice that the inter-pair constraint takes advantage of existing intra-pair constraint to minimize the number of constraints that must be added to routing engine. The least number of constraints will result in the best routing engine performance. This goal of least number of constraints comes at a cost. This structure assumes that the intra-pair skew tolerance is less than the inter-pair skew tolerance.

If we do a tolerance stackup analysis, we will see that this structure results in a case where the clk.N and the data[0].N may have up to 70 pS of skew.

In your application, this may not be acceptable. In that case, you may need to add additional constraints. Bear in mind that each constraint adds to the complexity of the problem the routing engine must solve.