#use-added-syntax(jitx)
defpackage main :
import core
import jitx
import jitx/commands
import ocdb/utils/generic-components
import helpers
; Define the shape/size of the board
val board-shape = RoundedRectangle(30.0, 18.5, 0.25)
; Setup the board
defn setup-board () :
set-board(ocdb/utils/defaults/default-board(ocdb/manufacturers/stackups/jlcpcb-jlc2313, board-shape))
set-rules(ocdb/manufacturers/rules/jlcpcb-rules)
pcb-module lm317a-regulator (output-voltage:Toleranced) :
pin vin
pin vout
pin gnd
pin adj
inst lm317a : ocdb/components/unisonic/LM317A/component
net (vin lm317a.input)
net (vout lm317a.output)
cap-strap(lm317a.input, gnd, 0.1e-6)
cap-strap(lm317a.output, gnd, 1.0e-6)
inst output-voltage-divider : ocdb/modules/passive-circuits/voltage-divider(in-voltage, adj-voltage, current) where :
val in-voltage = output-voltage
val adj-voltage = tol%(1.25, 15.0)
val current = 5.0e-3
net (output-voltage-divider.in lm317a.output)
net (output-voltage-divider.out lm317a.adj adj)
net (output-voltage-divider.lo gnd)
; Module to run as a design
pcb-module my-design :
val target-voltage = tol%(3.3, 10.0)
inst reg : lm317a-regulator(target-voltage)
; Write the board version on silkscreen
inst version-label : ocdb/artwork/board-text/version-silkscreen("Version 0.0")
place(version-label) at loc(0.0, height(board-shape) / 2.0 - 1.0) on Bottom
; Run the code
set-current-design("jitx-design") ;set the directory where the generated output will be placed
setup-board()
set-main-module(my-design)
; Use a helper function from helpers.stanza (use any helper function here)
; run-check-on-design(my-design)
; View the results
view-board()
view-schematic()
view-design-explorer()