timing

The timing statement is a means of applying a propagation time constraint to a signal topology. The idea is that for certain signals, we may want a particular signal to include a certain propagation delay from transmitter to receiver.

For example, in RGMII v1.3, the CLK signal requires a 1.5–2 nanosecond delay. The timing statement provides a way of informing the routing engine of this kind of constraint.

The timing statement is only valid within the pcb-module context.

These constraints are applied to the endpoints of a signal topology. The routing engine will infer that this constraint must be applied to every segment of the topology between the passed endpoints.

A timing statement is dependent on a structure statement to provide the conversion from route geometry to physical delay characteristics.

Signature

; Explicit Endpoint Form
timing(<REF-1>, <REF-2>) = <TimingConstraint>
; KeyValue Form
timing(<EXP>) = <TimingConstraint>

For the "Explicit Endpoint" form, the user provides a ref to a set of ports. The requirements for these ports are:

1. The <REF-*> must be a ref to a component, module, or abstract (require) port.
2. Each port must be a SinglePin port.

For the "KeyValue" form, the user can use the => operator to construct the endpoint expression. Each of the key and value ports must be a SinglePin port.

In its simplest form - the KeyValue expression looks something like this:

timing( <REF-1> => <REF-2> ) = <TimingConstraint>

The same requirements for <REF-*> defined in the Explicit Endpoint form exist for the KeyValue form.

Timing Constraint

The timing statement assigns a TimingConstraint object as a constraint to the topology.

defstruct TimingConstraint <: SignalConstraint :
  min-delay:Double
  max-delay:Double

defn TimingConstraint (delay: Toleranced) :
  ...

The min-delay and max-delay are relative delays limits in units of seconds.

The delay per unit length of a signal's route is determined by the Routing Structure applied via the structure statement. Without a structure statement that applies to the underlying topology.

Usage

Below is an example of using the timing constraint for one lane of an RGMII interface:

pcb-routing-structure se-50:
  ...

pcb-bundle rgmii-lane :
  port data : pin[4]
  port clk : pin
  port ctl : pin

pcb-component MCU:
  TX : rgmii-lane
  ...

pcb-component PHY:
  RX : rgmii-lane
  ...

pcb-module rgmii-example: 

  inst mcu : MCU
  inst phy : PHY

  topo-net(mcu.TX => phy.RX)

  structure(mcu.TX.data => phy.RX.data) = se-50
  structure(mcu.TX.clk => phy.RX.clk) = se-50
  structure(mcu.TX.ctl => phy.RX.ctl) = se-50

  ...

  val clk-delay = min-max(1.5e-9, 2.0e-9)
  timing(mcu.TX.clk => phy.RX.clk) = TimingConstraint(clk-delay)

Notes that this example uses the topo-net to construct the topology.

The timing statement above is equivalent to the following form:

  timing(mcu.TX.clk, mcu.RX.clk) = TimingConstraint(clk-delay)