`pcb-via`

The pcb-via statement is used to define a type of via that can instantiated in the board view. All via types are defined in code. This allows you to:

Create a known set of vias with particular characteristics
Create a known rule set for these vias to avoid deviations.
Maintain this via set and edit all vias of a particular type in one place.
Reuse existing via definition sets from project to project.

Outline

pcb-via via-name (arg1:Type1, ...) :
  name = <String>
  description = <String>
  start = <LayerIndex|Side>
  stop = <LayerIndex|Side>
  diameter = <Double>
  hole-diameter = <Double>
  type = <MechanicalDrill|LaserDrill>
  filled = <True|False>
  tented = <Side|Both|True|False>
  via-in-pad = <True|False>
  backdrill = <BackDrill|False>

The expression name via-name uniquely identifies this via definition in the current context.

The argument list (arg1:Type1, ...) is optional and provides a means of constructing parameterized via definitions.

Required Parameters
- start - Sets the starting layer for the via. Setting this to something other than the top layer allows for creating buried or blind vias.
- stop - Sets the ending layer for the via.
- diameter - Pad diameter in mm for the via
- hole-diameter - Drilled or Lasered hole diameter in mm for the via.
- type - Identifies the type of via, either mechanical drill or laser microvia.
Optional Parameters
- name - This name is used in the Board UI as a more user friendly name. If this string is not provided then the via-name expression is used as the via's name.
- description - This string is defining more meta-data for the via.
- filled - Indicates whether this via is filled or not.
- tented - Specifies whether or not there is a soldermask opening for this via on top, bottom, or both sides.
- via-in-pad - Specifies whether this via is allowed to be placed inside a component's pads.
- backdrill - Specifies whether or not this via is backdrilled See BackDrill

Usage

Here are a list of common examples:

Default Through-Hole

Here is a minimal example pcb-via statement:

pcb-via default-th:
  name = "Std TH"
  start = Top
  stop = Bottom
  diameter = 0.6 ; mm
  hole-diameter = 0.3 ; mm
  type = MechanicalDrill

This constructs what would be consided a typical through-hole via that traverses the board stackup from Top to Bottom layers.

Microvia - Top & Bottom

Here is a minimal example for a microvia on the top side of the board from the top layer to the first inner layer from the top:

public pcb-via top-uvia :
  name = "Top-0-1-uvia"
  start = LayerIndex(0, Top)
  stop = LayerIndex(1, Top)
  diameter = 0.15
  hole-diameter = 0.1
  type = LaserDrill
  tented = Top

Another Example but on the bottom side:

public pcb-via bot-uvia :
  name = "Bot-0-1-uvia"
  start = LayerIndex(1, Bottom)
  stop = LayerIndex(0, Bottom)
  diameter = 0.15
  hole-diameter = 0.1
  type = LaserDrill
  tented = Bottom

Notice that the LayerIndex when starting from the bottom of the board has the layer indices in the reverse order.

`pcb-via` with Arguments

Here is an example of constructing a pcb-via with arguments.

public pcb-via buried (st:Int, end:Int) :
  name = to-string("Buried-%_-%_" % [st, end])
  start = LayerIndex(st, Top)
  stop = LayerIndex(end, Top)
  diameter = 0.35
  hole-diameter = 0.2
  type = MechanicalDrill

Notice that I've used the name property so that different invokations of buried will construct uniquely named vias.

This via can then be used in the pcb-board definition like this:

public pcb-board mem-board :
  stackup = mem-stackup
  boundary = board-shape
  signal-boundary = board-shape
  vias = [default-th-via, top-uvia, bot-uvia, buried(1, 10)]

Notice that we pass the start and end layer for the buried via.

Watch Out!

There are a few things to look out for when defining vias:

Renaming a via definition in code can cause any instantiated vias in the board design to become invalid.
1. Invalid means that the via gets labeled with a red X
2. This only applies to vias that have been placed in the board view. If no vias of this type exist in the board yet, then this definition can be renamed at will.
3. Examples for changing a via name:
  1. If there is no name property and you change the via's expression name (ie change top-uvia to my-uvia from the above example)
  2. If there is no name property and you add a name property with a value that is different from the expression name.
  3. If there is an existing name property and you changed that string.
  4. If the name is defined via arguments to the definition and the arguments change.

JITX Documentation

pcb-via