#use-added-syntax(jitx)
defpackage check-report :
import core
import math
import jitx
import jitx/commands
import ocdb/utils/defaults
import ocdb/utils/generic-components
pcb-check aec-q200 (component:JITXObject):
#CHECK(
name = "Automotive rating"
description = "Check that a passive component is AEC Q200 rated"
condition = has-property?(component.aec-rating),
category = "Component Data"
subcheck-description = "Check that %_ has a defined aec-rating" % [ref(component)],
pass-message = "%_ has a property for aec-rating of %_" % [ref(component) property(component.aec-rating)],
info-message = "%_ does not have an aec-rating property attached" % [ref(component)],
locators = [instance-definition(component)]
)
#CHECK(
name = "Automotive rating"
description = "Check that a passive component is AEC Q200 rated"
condition = property(component.aec-rating) == "Q200",
category = "Component Checks"
subcheck-description = "Check that %_ is AEC Q200 rated." % [ref(component)],
pass-message = "%_ is AEC Q200 rated" % [ref(component)],
fail-message = "%_ is not AEC Q200 rated. Instead has rating %_." % [ref(component) property(component.aec-rating)],
locators = [instance-definition(component)]
)
defn check-aec (module:JITXObject) :
inside pcb-module:
for c in component-instances(self) do :
if has-property?(c.resistance) or reference-prefix?(c) == "R" or
has-property?(c.capacitance) or reference-prefix?(c) == "C" :
check aec-q200(c)
pcb-module checked-design :
inst r : chip-resistor(1.0)[10]
inst c : ceramic-cap(10.0e-6)[8]
for i in [0 1 3 4 5 7] do :
property(r[i].aec-rating) = "Q200"
property(c[i].aec-rating) = "Q200"
property(r[2].aec-rating) = "Q101"
check aec-q200(r[0])
check-aec(self)
set-current-design("test-checks")
make-default-board(checked-design, 4, Rectangle(25.0, 25.0))
; Show the Schematic and PCB for the design
view-board()
view-schematic()
run-checks("check-report.txt")