Ports
port
is a JITX statement that defines pins on components and modules that you can net to.
Syntax
port a : pin
pin a
port b : pin[6]
port c : pin[[1, 2, 4 through 6]]
port data : i2c
port lots-of-data : i2c[30]
Description
port a : pin
Create a port with a single pin named a
pin a
Create a port with a single pin named a
(same as above, but more convenient syntax.)
port b : pin[4]
Create a port named b
with 4 pins named b[0]
through b[3]
. You can loop over these pins programmatically:
for i in indices(b) do:
net (b[i])
println(i)
Prints out:
0
1
2
3
port c : pin[[1, 2, 4 through 6]]
Create a port named c
with a non-standard range. c
has 4 pins named c[1]
c[2]
c[4]
c[5]
and c[6]
. You can loop over these pins programmatically:
for i in indices(c) do:
net (c[i])
println(i)
Prints out:
1
2
4
5
6
port data : i2c
Create a port named data
of the pcb-bundle
named i2c
.
port lots-of-data : i2c[30]
Create a port array with 30 I2C ports. lots-of-data[0].sda
is the sda
pin of the first I2C bundle.