#use-added-syntax(jitx)
defpackage main :
import core
import jitx
import jitx/commands
import ocdb/utils/generic-components
import helpers
; Define the shape/size of the board
val board-shape = RoundedRectangle(35.0, 25.0, 0.25)
; Setup the board
defn setup-board () :
set-board(ocdb/utils/defaults/default-board(ocdb/manufacturers/stackups/jlcpcb-jlc2313, board-shape))
set-rules(ocdb/manufacturers/rules/jlcpcb-rules)
pcb-module lm317a-regulator (output-voltage:Toleranced) :
pin vin
pin vout
pin gnd
pin adj
inst lm317a : ocdb/components/unisonic/LM317A/component
net (vin lm317a.input)
net (vout lm317a.output)
cap-strap(lm317a.input, gnd, 0.1e-6)
cap-strap(lm317a.output, gnd, 1.0e-6)
inst output-voltage-divider : ocdb/modules/passive-circuits/voltage-divider(source-voltage = in-voltage, divider-output = adj-voltage, current = current) where :
val in-voltage = output-voltage
val adj-voltage = tol%(1.25, 15.0)
val current = 5.0e-3
; inside pcb-module lm317a-regulator
schematic-group(self) = lm317a
layout-group(self) = lm317a
net (output-voltage-divider.in lm317a.output)
net (output-voltage-divider.out lm317a.adj adj)
net (output-voltage-divider.lo gnd)
; Module to run as a design
pcb-module my-design :
val target-voltage = tol%(3.3, 10.0)
inst reg : lm317a-regulator(target-voltage)
; Write the board version on silkscreen
inst version-label : ocdb/artwork/board-text/version-silkscreen("Version 0.0")
place(version-label) at loc(0.0, height(board-shape) / 2.0 - 1.0) on Bottom
inst source : banana-plug-module() ; shortcut to instantiate and place two `banana-plug`s plus the electrical support
net gnd (reg.gnd, source.power.gnd)
net vin (reg.vin, source.power.vdd)
inst measure : bnc-connector()
net vout (reg.vout, measure.sig)
net (gnd, measure.gnd)
val test-points = add-testpoint([reg.adj, gnd])
val target-current = 450.0e-3
val target-load = closest-std-val(typ-value(target-voltage) / target-current, 5.0)
inst load : chip-resistor(["resistance" => target-load, "min-rated-power" => typ-value(target-voltage) * target-current * 2.0 ])
net (load.p[1], reg.vout)
net (load.p[2], gnd)
symbol(gnd) = ocdb/utils/symbols/ground-sym ; has to be placed after the definition of the net itself
symbol(vout) = ocdb/utils/symbols/supply-sym ; has to be placed after the definition of the net itself
; add a ground plane
geom(gnd) :
copper-pour(LayerIndex(1), isolate = 0.1, rank = 1, orphans = true) = Rectangle(width(board-shape) - 1.0, height(board-shape) - 1.0)
; add a net class for power nets
val power-net-class = NetClass(`Power, [`min-trace => 0.381])
property(gnd.net-class) = power-net-class
property(vout.net-class) = power-net-class
property(vin.net-class) = power-net-class
; inside pcb-module my-module
schematic-group([test-points, measure]) = test
layout-group([test-points, measure]) = test
;inside pcb-module my-module
schematic-group(load) = schematic-group(reg)
layout-group(load) = layout-group(reg)
; Run the code
set-current-design("jitx-design") ;set the directory where the generated output will be placed
setup-board()
set-use-layout-groups()
set-main-module(my-design)
; Use a helper function from helpers.stanza (use any helper function here)
; run-check-on-design(my-design)
; View the results
view-board()
view-schematic()
view-design-explorer()