#use-added-syntax(jitx)
defpackage first-design :
  import core
  import jitx
  import jitx/commands

pcb-component photodiode :
  port a 
  port c

pcb-component op-amp :
  port in+ 
  port in- 
  port out 
  port v+  
  port v-  

pcb-component three-pin-header :
  port p : pin[3]

pcb-module my-design :
  inst d : photodiode
  inst opa : op-amp
  inst connector : three-pin-header

  ; Set up power connections
  net GND (opa.v- connector.p[0])
  public net VDD (opa.v+ connector.p[1])

  ; Connect op-amp
  net (d.c opa.in-)
  net (GND opa.in+ d.a)

for p in refs(my-design.VDD) do :
  println(ref(p))