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jsl/protocols/memory/gddr7

Package name: jsl/protocols/memory/gddr7

Graphics Double Data Rate 7 protocol (GDDR7)

GDDR7 is a high speed memory protocol

References

  • https://en.wikipedia.org/wiki/GDDR7_SDRAM

This functions and definitions in this file support defining GDDR7 connections between microprocessors and memories in a board design.

The standard defines some of the bounds on the intra-pair skew timing and maximum loss. The values in this file are toleranced values with upper/lower limits for the intra-pair skew and the maximum loss as a double representing dB. Some defaults in this file are derived from the references listed below.

  1. Skew match for RCK_P RCK_N is 0.0 ± 10.0e-15 (10 fs)
  2. Skew match for WCK_P WCK_N is 0.0 ± 10.0e-15 (10 fs)
  3. Skew match between RCK and WCK is 0.0 ± 20.0e-12 (20 ps)
  4. Skew match between WCK and CA (per channel A,B,C,D) is 0.0 ± 20.0e-12 (20 ps)
  5. Skew match between RCK and DQ and DQE (per channel A,B,C,D) is 0.0 ± 20.0e-12 (20 ps)
  6. Skew match between WCK and DQ and DQE (per channel A,B,C,D) is 0.0 ± 20.0e-12 (20 ps)
  7. Skew match between DQ and DQE (per channel A,B,C,D) is 0.0 ± 5.0e-12 (5 ps)
  8. Skew match between Reset and CA (per channel A,B,C,D) is 0.0 ± 100.0e-12 (100ps)
  9. Skew match between ERR and WCK (per channel A,B,C,D) is 0.0 ± 100.0e-12 (100 ps)
  10. Skew match between CA (per channel A,B,C,D) is 0.0 ± 5.0e-12 (5ps)
  11. Maximum loss for all signals is 5.0 dB at Nyquist frequency
  12. Differential impedance for RCK and WCK is 100 ohms ± 10%
  13. Single-ended impedance for DQ, DQE, CA, and ERR is 50 ohms ± 10%

Calculating the distance to time correspondence depends on the board material. Example: tpd 147 ps/in 170 ps/in -> 147 fs/mil to 170 fs/mil @ 5 mils spec'ed that is a intra-pair skew of 750 fs to 850 fs @ 10 mils spec'ed that is a intra-pair skew of 1.50 ps to 1.70 ps

Summary

GDDR7-Constraint

GDDR7 SI Constraint Type

Constructors

Function Description
GDDR7-Constraint Constructor for defstruct GDDR7-Constraint

Methods

Function Description
constrain Constrain a GDDR7 Link

Functions

Function Description
GDDR7-Constraint Constructor for the GDDR7 Link Constraint

General Definitions

Function Description
gddr7-data-channel GDDR7 Data Bundle
gddr7-b
gddr7-control-channel GDDR7 Control Bundle
connect-GDDR7 This function connects a GDDR7 (Graphics Double Data Rate 7) link between two components, 'src' and 'dst', using specified routing structures. It applies the necessary constraints for proper GDDR7 signal integrity, including differential pair constraints, timing windows, and loss limits for various signals such as RCK (Read Clock), WCK (Write Clock), DQ (Data), CA (Command/Address), and ERR (Error) lines.
gddr7-get-trace-impedance Differential impedance specified by the GDDR7 standard
gddr7 GDDR7 Bundle

Definitions

GDDR7-Constraint

GDDR7 SI Constraint Type

public defstruct GDDR7-Constraint <: SI-Constraint
    diff-route-struct: DifferentialRoutingStructure
    loss: Double
    se-route-struct: RoutingStructure
    skew-ca: Toleranced
    skew-dq: Toleranced
    skew-err-wck: Toleranced
    skew-rck: Toleranced
    skew-rck-dq: Toleranced
    skew-rck-wck: Toleranced
    skew-rst-ca: Toleranced
    skew-wck: Toleranced
    skew-wck-ca: Toleranced
    skew-wck-dq: Toleranced

  • diff-route-struct: DifferentialRoutingStructure - Differential Routing Structure for each Diff-Pair

  • loss: Double - Diff-Pair Max Loss Limit Constraint in dB

  • se-route-struct: RoutingStructure - Single-Ended Routing Structure for each SE signal

  • skew-ca: Toleranced - CA Inter-pair Timing Skew Constraint in Seconds

  • skew-dq: Toleranced - DQ and DQE Inter-pair Timing Skew Constraint in Seconds

  • skew-err-wck: Toleranced - ERR and WCK Inter-pair Timing Skew Constraint in Seconds

  • skew-rck: Toleranced - RCK Intra-pair Timing Skew Constraint in Seconds

  • skew-rck-dq: Toleranced - RCK to DQ/DQE Inter-pair Timing Skew Constraint in Seconds

  • skew-rck-wck: Toleranced - RCK to WCK Inter-pair Timing Skew Constraint in Seconds

  • skew-rst-ca: Toleranced - Reset to CA Inter-pair Timing Skew Constraint in Seconds

  • skew-wck: Toleranced - WCK Intra-pair Timing Skew Constraint in Seconds

  • skew-wck-ca: Toleranced - WCK to CA Inter-signal Timing Skew Constraint in Seconds

  • skew-wck-dq: Toleranced - WCK to DQ/DQE Inter-pair Timing Skew Constraint in Seconds

This derives from the whole data lane constraint as most of the controlled signals are single-ended but referenced to the read and write clock lane pairs (tx/rx). All of these constraints will be applied to the full lane. 0.0 ± 10.0e-15, ; Skew match for RCK_P RCK_N is 0.0 ± 10.0e-15 (10 fs) 0.0 ± 10.0e-15, ; Skew match for WCK_P WCK_N is 0.0 ± 10.0e-15 (10 fs) 0.0 ± 20.0e-12, ; Skew match between RCK and WCK is 0.0 ± 20.0e-12 (20 ps) 0.0 ± 20.0e-12, ; Skew match between WCK and CA (per channel A,B,C,D) is 0.0 ± 20.0e-12 (20 ps) 0.0 ± 20.0e-12, ; Skew match between RCK and DQ and DQE (per channel A,B,C,D) is 0.0 ± 20.0e-12 (20 p 0.0 ± 20.0e-12, ; Skew match between WCK and DQ and DQE (per channel A,B,C,D) is 0.0 ± 20.0e-12 (20 p 0.0 ± 5.0e-12, ; Skew match between DQ and DQE (per channel A,B,C,D) is 0.0 ± 5.0e-12 (5 ps) 0.0 ± 100.0e-12,; Skew match between Reset and CA (per channel A,B,C,D) is 0.0 ± 100.0e-12 (100ps) 0.0 ± 100.0e-12,; Skew match between ERR and WCK (per channel A,B,C,D) is 0.0 ± 100.0e-12 (100 ps) 0.0 ± 5.0e-12, ; Skew match between CA (per channel A,B,C,D) is 0.0 ± 5.0e-12 (5ps)

The constrain function for this type expects two compatible gddr7-b types.

Constructors

GDDR7-Constraint

Constructor for defstruct GDDR7-Constraint

public defn GDDR7-Constraint ( -- skew-rck:Toleranced = ?, skew-wck:Toleranced = ?, skew-rck-wck:Toleranced = ?, skew-wck-ca:Toleranced = ?, skew-rck-dq:Toleranced = ?, skew-wck-dq:Toleranced = ?, skew-dq:Toleranced = ?, skew-rst-ca:Toleranced = ?, skew-err-wck:Toleranced = ?, skew-ca:Toleranced = ?, loss:Double = ?, diff-route-struct:DifferentialRoutingStructure, se-route-struct:RoutingStructure)

Methods

constrain

Constrain a GDDR7 Link

defmethod constrain (cst:GDDR7-Constraint, src:JITXObject, dst:JITXObject) -> False

  • cst: GDDR7-Constraint - Constraint Object
  • src: JITXObject - Source End Point - must be of gddr7-b type
  • dst: JITXObject - Destination End Point - must be of gddr7-b type and match the parameterization of src, including lane counts.
  • Returns False

Functions

GDDR7-Constraint

Constructor for the GDDR7 Link Constraint

public defn GDDR7-Constraint (diff-rs:DifferentialRoutingStructure, rs:RoutingStructure) -> GDDR7-Constraint

  • rs: RoutingStructure - Differential Routing Structure constraints for all data lane signals, command/address, and the differential write and read clocks. This is not applied to the control signals.
  • Returns GDDR7-Constraint

General Definitions

gddr7-data-channel

GDDR7 Data Bundle One GDDR7 data bundle consists of the data connections between an integrated memory controller and one GDDR7 memory chip.

public pcb-bundle gddr7-data-channel

  • DQ - Data bit

  • RCK - Read clock

  • WCK - Write clock

  • CA - Address bit

  • DQE - Data bit error detection

  • ERR - Error flag

gddr7-b

public pcb-bundle gddr7-b ()

gddr7-control-channel

GDDR7 Control Bundle One GDDR7 control bundle consists of the control connections between an integrated memory controller and one GDDR7 memory chip.

public pcb-bundle gddr7-control-channel

  • RESET_n - Reset signal

  • ZQ_AB - Impedance calibration for channels A and B

  • ZQ_CD - Impedance calibration for channels C and D

connect-GDDR7

This function connects a GDDR7 (Graphics Double Data Rate 7) link between two components, 'src' and 'dst', using specified routing structures. It applies the necessary constraints for proper GDDR7 signal integrity, including differential pair constraints, timing windows, and loss limits for various signals such as RCK (Read Clock), WCK (Write Clock), DQ (Data), CA (Command/Address), and ERR (Error) lines.

public defn connect-GDDR7 (src:JITXObject, dst:JITXObject, diff-rs:DifferentialRoutingStructure, rs:RoutingStructure)

gddr7-get-trace-impedance

Differential impedance specified by the GDDR7 standard This is a helper function that returns the expected differential trace impedance for the standard.

public defn gddr7-get-trace-impedance () -> [Toleranced, Toleranced]

  • Returns [Toleranced, Toleranced] - Upper/lower limits for the impedance.

gddr7

GDDR7 Bundle One GDDR7 bundle consists of the connections between an integrated memory controller and one GDDR7 memory chip. The overall memory connections consists of 4 separate channels.

public defn gddr7 ()

  • control - Control channel for GDDR7

  • data - Four data channels for GDDR7