comms¶

Package name: jsl/bundles/comms

Summary¶

Data Types¶

SPIPins ¶

SPI Bundle Pin Names

Functions¶

Function	Description
wide-spi	Wide-SPI Bundle
octal-spi	Octal SPI Bundle Generator
dual-spi	Dual SPI Bundle Generator
spi	SPI Bundle Generator
quad-spi	Quad SPI Bundle Generator

SMBUSPins ¶

SMBus Bundle

Functions¶

Function	Description
smbus	Configurable SMBus Bundle

UARTPins ¶

Functions¶

Function	Description
uart	UART Bundle Generator

MicrowirePins ¶

Optional Pins in the Microwire Bundle Construction

Functions¶

Function	Description
microwire	Microwire serial communciation protocol
microwire-b	Microwire serial communciation protocol

General Definitions¶

Function	Description
std-spi	Standard SPI Generator
can-phy	CAN Physical Layer Bundle
i2s	Inter-Integrated Sound - I2S Protocol
can-logical	CAN Logical Interface Bundle
octal-spi-with-cs-dqs	Octal SPI Bundle with Chip Select and Data Strobe
microwire-4	Microwire serial communciation protocol
microwire-3wire	Microwire serial communciation protocol
spi-with-cs	Standard SPI with Chip Select Generator
i2c	I2C Bundle
minimal-uart	Minimal UART Bundle Generator
std-smbus	Standard SMBUS Generator
uart-fc	Uart with RTS/CTS Flow Control

Definitions¶

SPIPins¶

SPI Bundle Pin Names

public defenum SPIPins <: Equalable & Hashable & JITXValue

SPI-CS
SPI-COPI
SPI-CIPO

A list of possible names for the SPI interface. Note that in order to connect SPI interfaces automatically, the constituent pins need to be present on all objects to be connected.

Functions¶

wide-spi¶

Wide-SPI Bundle

public defn wide-spi (width:Int, pins:Collection<SPIPins>)

width: Int - Number of datalines to include in this bundle. Common values are 2, 4, and 8
pins: Collection<SPIPins> - Optionally allow for Chip Select pin on this interface. Note CIPO and COPI are not supported.

sck - Synchronous Clock Line
cs - Chip Select
data - Variable Width Data Bus depending on width parameter

This bundle is used to define bundles for multi-data-line SPI busses. These are often seen for high bandwidth comms interfaces or on flash chips.

octal-spi¶

Octal SPI Bundle Generator

public defn octal-spi (pins:SPIPins ...)

sck - Synchronous Clock Line
cs - Chip Select
data - Data Bus of width=8

dual-spi¶

Dual SPI Bundle Generator

public defn dual-spi (pins:SPIPins ...)

sck - Synchronous Clock Line
cs - Chip Select
data - Data Bus of width=2

spi¶

SPI Bundle Generator

public defn spi (pins:SPIPins ...)

pins: SPIPins - User needs to specify which pins will be included in the SPI interface. Some devices don't have a MISO pin for example.

sck - Synchronous Clock Line
cs - Chip Select
cipo - Controller In Peripheral Out
copi - Controller Out Peripheral In

Serial Peripheral Interface is a serial communication protocol.

References¶

https://en.wikipedia.org/wiki/Serial_Peripheral_Interface

quad-spi¶

Quad SPI Bundle Generator

public defn quad-spi (pins:SPIPins ...)

sck - Synchronous Clock Line
cs - Chip Select
data - Data Bus of width=4

SMBUSPins¶

SMBus Bundle

public defenum SMBUSPins <: Equalable & Hashable & JITXValue

SMBALERT#
SMBSUS#

System Management Bus (SMBus) is a two wire serial communication protocol

References¶

http://smbus.org/specs/

Functions¶

smbus¶

Configurable SMBus Bundle

public defn smbus (pins:SMBUSPins ...)

pins: SMBUSPins - Optional pins that can be included in the bundle.

smbclk - Synchronous Clock Line
smbdat - Synchronous Data Line
smbalert# - Optional Alert Interrupt - Active Low
smbsus# - Optional Suspend Line - Active Low

  val b = smbus(SMBALERT#)
  supports b:
    b.smbclk => self.CLK
    b.smbdat => self.DAT
    b.smbalert# => self.ALERT_n

Adding the SMBALERT# value to the function definition

generates a pcb-bundle including the base pins smbclk and smbdat as well as the optional smbalert# pin.

UARTPins¶

public defenum UARTPins <: Equalable & Hashable & JITXValue

UART-DTR
UART-CTS
UART-DCD
UART-RI
UART-DSR
UART-RTS
UART-CK
UART-DE
UART-RX
UART-TX

Functions¶

uart¶

UART Bundle Generator

public defn uart (pins:UARTPins ...)

tx - Transmit Data Line
rx - Receive Data Line
cts - Clear to Send Line
rts - Ready to Send Line
dtr - Data Terminal Ready Line
dsr - Data Set Ready Line
dcd - Data Carrier Detect Line
ri - Ring Indicator Line
ck - Clock Line
de - Driver Enable Line

Universal Asynchronous Receiver/Transmitter Constructs a bundle with the passed pin configuration

References¶

https://en.wikipedia.org/wiki/Universal_asynchronous_receiver-transmitter

MicrowirePins¶

Optional Pins in the Microwire Bundle Construction

public defenum MicrowirePins <: Equalable & Hashable & JITXValue

Microwire-CS - Includes the Chip Select Port
Microwire-DO - Includes the Data Output Port
Microwire-DI - Includes the Data Input Port

Functions¶

microwire¶

Microwire serial communciation protocol

public defn microwire (opts:MicrowirePins ...)

opts: MicrowirePins - Set of optional ports to include in this bundle definition. Duplicates are not allowed.

clk - Synchronous clock - Required Port
cs - Chip Select - Optional Port
do - Data Output - Optional Port
di - Data Input - Optional Port

Microwire is a subset of SPI with slightly different latching requirements. It often comes in a 3-wire variant.

microwire-b¶

Microwire serial communciation protocol

public defn microwire-b (opts:Collection<MicrowirePins>)

opts: Collection<MicrowirePins> - Set of optional ports to include in this bundle definition. Duplicates are not allowed.

clk - Synchronous clock - Required Port
cs - Chip Select - Optional Port
do - Data Output - Optional Port
di - Data Input - Optional Port

Microwire is a subset of SPI with slightly different latching requirements. It often comes in a 3-wire variant.

General Definitions¶

std-spi¶

Standard SPI Generator

public defn std-spi ()

sck - Synchronous Clock Line
cipo - Controller In Peripheral Out
copi - Controller Out Peripheral In

This generator will construct an SPI bundle with the following pins:

can-phy¶

CAN Physical Layer Bundle

public pcb-bundle can-phy

H - High side of the differential pair for the transmission line
L - Low side of the differential pair for the transmission line

This bundle defines the physical layer for the CAN interface which consists of a differential pair H / L

i2s¶

Inter-Integrated Sound - I2S Protocol

public pcb-bundle i2s

sck - Serial Interface Clock
ws - Word Select - typically for left vs right differentiation
sd - Data Signal

The I2S protocol is a synchronous serial communication protocol similar to SPI

Originally Specification was from Phillips. Current specification is present in NXP's references

References¶

https://www.nxp.com/docs/en/user-manual/UM11732.pdf

can-logical¶

CAN Logical Interface Bundle

public pcb-bundle can-logical

rx - Receive line
tx - Transmit line

This interface from a microcontroller to the PHY is typically a two wire interface consisting of a TX and RX line.

TODO - Add optional error line ?

octal-spi-with-cs-dqs¶

Octal SPI Bundle with Chip Select and Data Strobe

public pcb-bundle octal-spi-with-cs-dqs

sck - Synchronous Clock Line
cs - Chip Select
dqs - Data Strobe
data - Data Bus of width=8

microwire-4¶

Microwire serial communciation protocol

public defn microwire-4 ()

clk - Synchronous clock
cs - Chip Select
do - Data Output
di - Data Input

Microwire is a subset of SPI with slightly different latching requirements.

This implementation provides the full 4-wire interface.

microwire-3wire¶

Microwire serial communciation protocol

public defn microwire-3wire ()

clk - Synchronous clock
cs - Chip Select
do - Data Output/Input

Microwire is a subset of SPI with slightly different latching requirements.

This is a 3-wire variant where do is is typically a bidirectional data wire.

spi-with-cs¶

Standard SPI with Chip Select Generator

public defn spi-with-cs ()

sck - Synchronous Clock Line
cs - Chip Select
cipo - Controller In Peripheral Out
copi - Controller Out Peripheral In

This generator will construct an SPI bundle with the following pins:

i2c¶

I2C Bundle

public pcb-bundle i2c

sda - Synchronous Data Line
scl - Synchronous Clock Line

Inter-Integrated Circuit (I2C) is a serial communication protocol

References¶

https://en.wikipedia.org/wiki/I%C2%B2C

minimal-uart¶

Minimal UART Bundle Generator

public defn minimal-uart ()

tx - Transmit Data Line
rx - Receive Data Line

This generator constructs a UART bundle consisting of:

std-smbus¶

Standard SMBUS Generator

public defn std-smbus ()

smbclk - Synchronous Clock Line
smbdat - Synchronous Data Line

This generator will construct an SMBUS bundle with the following pins:

uart-fc¶

Uart with RTS/CTS Flow Control

public defn uart-fc ()

tx - Transmit Data Line
rx - Receive Data Line
rts - Ready to Send
cts - Clear to Send

Forwarded by package: jsl/bundles

jsl/bundles/comms¶

Summary¶

Data Types¶

SPIPins¶

Functions¶

SMBUSPins¶

Functions¶

UARTPins¶

Functions¶

MicrowirePins¶

Functions¶

General Definitions¶

Definitions¶

SPIPins¶

Functions¶

wide-spi¶

octal-spi¶

dual-spi¶

spi¶

References¶

quad-spi¶

SMBUSPins¶

References¶

Functions¶

smbus¶

UARTPins¶

Functions¶

uart¶

References¶

MicrowirePins¶

Functions¶

microwire¶

microwire-b¶

General Definitions¶

std-spi¶

can-phy¶

i2s¶

References¶

can-logical¶

octal-spi-with-cs-dqs¶

microwire-4¶

microwire-3wire¶

spi-with-cs¶

i2c¶

References¶

minimal-uart¶

std-smbus¶

uart-fc¶

Related Packages¶

SPIPins ¶

SMBUSPins ¶

UARTPins ¶

MicrowirePins ¶