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jsl/protocols/pcie

Package name: jsl/protocols/pcie

PCI-e Protocol

PCI-e is a serial communication supporting high speed data links

References

  • https://en.wikipedia.org/wiki/PCI_Express

This functions and definitions in this file support defining PCI-e connections between components in a board design.

PCIe Blocking Capacitors

The PCIe specification calls for AC coupling for the data lanes. This is typically achieved using a blocking capacitor. When connecting two active components, this typically means blocking caps from Tx -> Rx on both sides of the link. When connecting an active component to a passive component, this typically means adding the blocking caps only on the Tx -> Rx side of the link.

The functions in this module allow you to pass a blocking capacitor as an Instantiable. This component will get instantiated for each leg of the diff-pair. These functions handle the topology configuration, but the user needs to set a pin-model statement on the capacitor component.

Summary

Data Types

PCIeVersion

PCI-e Generation enums This is a fixed list of possible generation definitions for PCIe Can be extended if needed to include PCIE-V3.1, for example

Functions

Function Description
PCIe-Constraint Constructor for the PCIe Link Constraint
pcie-get-trace-impedance Differential impedance specified by the PCIe standard
pcie-get-skew-loss-vals Curated values for skew and loss of PCIe Channel

PCIe-Constraint

PCIe SI Constraint Type

Constructors

Function Description
PCIe-Constraint Constructor for defstruct PCIe-Constraint

Methods

Function Description
constrain Constrain a PCIe Link

Functions

Function Description
PCIe-Constraint Constructor for the PCIe Link Constraint

PCIePins

Functions

Function Description
pcie-b
pcie PCI-e Bundle
pcie-control PCI-e Control bundle

PCIeWidth

PCI-e Width enums This is a fixed list of possible lane widths for PCIe

Functions

Function Description
PCIe-enum-to-int

General Definitions

Function Description
pcie-data PCI-e Data Bundle
reverse-pcie-lanes Reverse the PCIe Connection using a node

Definitions

PCIeVersion

PCI-e Generation enums This is a fixed list of possible generation definitions for PCIe Can be extended if needed to include PCIE-V3.1, for example

public defenum PCIeVersion <: Equalable & Hashable & JITXValue

  • PCIE-V1

  • PCIE-V2

  • PCIE-V3

  • PCIE-V4

  • PCIE-V5

  • PCIE-V6

  • PCIE-V7

Functions

PCIe-Constraint

Constructor for the PCIe Link Constraint

public defn PCIe-Constraint (v:PCIeVersion, rs:DifferentialRoutingStructure) -> PCIe-Constraint

  • v: PCIeVersion - PCIe Version that we are building
  • rs: DifferentialRoutingStructure - Differential Routing Structure constraints for all lane pairs and the refclk. This is not applied to the control signals.
  • Returns PCIe-Constraint

pcie-get-trace-impedance

Differential impedance specified by the PCIe standard This is a helper function that returns the expected differential trace impedance for the specified generation of the PCIe standard.

public defn pcie-get-trace-impedance (gen:PCIeVersion) -> Toleranced

  • Returns Toleranced - Upper/lower limits for the impedance.

pcie-get-skew-loss-vals

Curated values for skew and loss of PCIe Channel This is a helper function that returns the bounds on the intra-pair skew timing and maximum loss as expected by the particular standard targeted by the user.The values returned are a toleranced value with upper/lower limits for the intra-pair skew and the maximum loss as a double representing dB. Some defaults in the table are derived from the references listed below. https://pcisig.com/pci-express%C2%AE-50-architecture-channel-insertion-loss-budget-0

There is also a very loose lane to lane skew spec for different lane rates: | Parameter | 2.5 GT/s | 5.0 GT/s | 8.0 GT/s | 16.0 GT/s | Unit | |------------------|----------|----------|----------|-----------|-------| |Lane to Lane Skew | 20 | 8 | 6 | 5 | ns |

Calculating the intra-pair skew distance to time correspondence depends on the material. tpd 147 ps/in 170 ps/in -> 147 fs/mil to 170 fs/mil @ 5 mils spec'ed that is a intra-pair skew of 750 fs to 850 fs @ 10 mils spec'ed that is a intra-pair skew of 1.50 ps to 1.70 ps for system board skew match: page 2 of @see https://docs.broadcom.com/doc/pcie-pcb-layout-review

Another good reference:

public defn pcie-get-skew-loss-vals (gen:PCIeVersion) -> [Toleranced, Double]

  • Returns [Toleranced, Double]
References
  • https://community.nxp.com/pwmxy87654/attachments/pwmxy87654/powerquicc/2284/1/AN307_TP_HARDWARE_DESIGN_PCI_SMGIII.pdf

PCIe-Constraint

PCIe SI Constraint Type

public defstruct PCIe-Constraint <: DiffPair-Constraint :

This derives from the differential pair constraint as most of the controlled signals are differential lane pairs (tx/rx). All of these constraints will be applied to all of the pairs.

The constrain function for this type expects two compatible pcie-b types.

Constructors

PCIe-Constraint

Constructor for defstruct PCIe-Constraint

public defn PCIe-Constraint ( -- skew:Toleranced, loss:Double, route-struct:DifferentialRoutingStructure)

Methods

constrain

Constrain a PCIe Link

defmethod constrain (cst:PCIe-Constraint, src:JITXObject, dst:JITXObject) -> False

  • cst: PCIe-Constraint - Constraint Object
  • src: JITXObject - Source End Point - must be of pcie-b type
  • dst: JITXObject - Destination End Point - must be of pcie-b type and match the parameterization of src, including lane counts.
  • Returns False

Functions

PCIe-Constraint

Constructor for the PCIe Link Constraint

public defn PCIe-Constraint (v:PCIeVersion, rs:DifferentialRoutingStructure) -> PCIe-Constraint

  • v: PCIeVersion - PCIe Version that we are building
  • rs: DifferentialRoutingStructure - Differential Routing Structure constraints for all lane pairs and the refclk. This is not applied to the control signals.
  • Returns PCIe-Constraint

PCIePins

public defenum PCIePins <: Equalable & Hashable & JITXValue

  • PCIe-PRSNT#

Functions

pcie-b

public defn pcie-b (lanes:Int, opt-pins:Collection<PCIePins>)

pcie

PCI-e Bundle The Data Bundle consists of a number (1 or more) of RX and TX pairs (1 RX/TX pair set = 1 lane) and it also includes a refclk (100MHz) differential pair

public defn pcie (lanes:Int, opt-pins:PCIePins ...)

  • lanes: Int - The number of lanes to be configured for this bundle.
  • opt-pins: PCIePins - Optional pin support where the value is an enum from jsl/bundles/pcie/PCIePins

  • control - Control channel for PCIe

  • data - Data channel for PCIe

pcie-control

PCI-e Control bundle PCI-e is a serial communication supporting high speed data links

public defn pcie-control (pins:Collection<PCIePins>)

  • pins: Collection<PCIePins> - An optional set of pins to be implemented in the control bundle

  • PEWAKE#

  • PERST#

  • CLKREQ#

  • PRSNT# - Optional signal

PCIeWidth

PCI-e Width enums This is a fixed list of possible lane widths for PCIe

public defenum PCIeWidth <: Equalable & Hashable & JITXValue

  • PCIe-x1

  • PCIe-x2

  • PCIe-x4

  • PCIe-x8

  • PCIe-x16

  • PCIe-x32

Functions

PCIe-enum-to-int

public defn PCIe-enum-to-int (en:PCIeWidth) -> Int

  • Returns Int

General Definitions

pcie-data

PCI-e Data Bundle The Data bundle consists of a number (1 or more) of RX and TX pairs (1 RX/TX pair set = 1 lane) and it also includes a refclk (100MHz) differential pair.

public pcb-bundle pcie-data (lanes:Int)

  • lanes: Int - The number of lanes in the bundle.

  • rx - The receive diff-pair (# of lanes wide)

  • tx - The transmit diff-pair (# of lanes wide)

reverse-pcie-lanes

Reverse the PCIe Connection using a node

public defn reverse-pcie-lanes (p:JITXObject)

  • p: JITXObject - Input port bundle as a pcie-b bundle

When connecting two active PCIe devices, you will often need to create a null modem style connection instead of the default tx => tx and rx => rx.

This function allows for a convenient way to create tx => rx and rx => tx lane connections.

Related Packages

Forwarded by package: jsl/protocols