Spice

spice is a JITX statement that associates SPICE code with a pcb-component. These SPICE snippets are extracted and compiled together to produce a global SPICE netlist for the design. Currently the NGSPICE syntax is supported.

Syntax

pcb-component one-k-resistor :
  port p[1]
  port p[2]
  spice:
    "[R] {p[1]} {p[2]} 1000"

pcb-component electrolytic-capacitor (capacitance:Double, ESR:Double) :
  port a
  port c
  spice:
    "[C] {p[1]} tmp {capacitance}"
    "[R] tmp {p[2]} {ESR}"

pcb-component npn-transistor :
  port b
  port e
  port c
  spice :
    "[X] {c} {b} {e} PMBT3904"

pcb-module main-design:
  inst amp : {class-a-amplifier(2.0e3)}

  spice:
  "[Vi] {amp.in} {power.src.gnd} SIN(0 1 1k 0 0)"
  "plot(v({amp.out}))
  ".temp 80.0"
  ".tran 0.01ms 5m"

Description

The spice statement creates an block of syntax where each line will correspond to a line in the global spice netlist. Parametric objects such as references to ports, or numeric values are escaped with curly braces { }. The following snippet defines the spice netlist of this component to be a 1000.0 Ohm resistor between component pins p[1] and p[2]

pcb-component one-k-resistor :
  port p[1]
  port p[2]
  spice:
    "[R] {p[1]} {p[2]} 1000.0"

The following snippet is similar, but shows how we can build up a netlist with temporary nodes, and use curly braces to make the SPICE model parametric.

pcb-component electrolytic-capacitor (capacitance:Double, ESR:Double) :
  port a
  port c
  spice:
    "[C] {a} tmp {capacitance}"
    "[R] tmp {c} {ESR}"

This snippet shows how we could use an externally defined/manufacturer provided spice model and map it to the pins of the component. Beware that some manufacturer-provided models are incorrect, and/or will cause convergence issues in simulation.

pcb-component npn-transistor :
  port b
  port e
  port c
  spice :
    "[X] {c} {b} {e} PMBT3904"

We can also use the spice statement in pcb-modules to define a spice subcircuit for an entire module. Here we use it in the main module to connect a voltage input to an amplifier, plot the voltage of the output, and set the simulation parameters for the entire design.

pcb-module main-design:
  inst amp : {class-a-amplifier(2.0e3)}

  spice:
  "[Vi] {amp.in} {power.src.gnd} SIN(0 1 1k 0 0)"
  "plot(v({amp.out}))"
  ".temp 80.0"
  ".tran 0.01ms 5m"