proof module

JS4 verification designs: code routes that pick, or break, a pin assignment.

Not part of the shipping design. Each adds code Routes to JS4Circuit for one byte lane, the clock, the clock enable and one address bit of channel B, and nothing else:

• JS4ProofDesign routes a legal assignment. Memory byte 2 (channel B, DQ16 to DQ23) lands in byte slot 3, the slot OPTIMUM_X32_FLIPPED gives byte 3 by default, so the routes choose a byte swap (rule 4) and a reordering of the eight DQ (rule 3). JITX resolves the provide options from the routes and measures each routed path: DQS and CK intra-pair skew, each DQ and DMI against DQS, CA0 and both CKE balls against CK, and the CK minus DQS window. The CKE runs in a chain, FPGA pin to CKE0 to CKE1.

• JS4IllegalDesign routes the same set but sends one DQ bit to a pin of byte slot 0, a channel A slot. No option allows that, so the route is dropped and the path stays unassigned.

What the proof shows is that the constraints bind: each routed path reports a measured skew. It does not show compliance:

• The routes run on inner layers, as UG863 asks: the DQS pair, two DQ bits and the CKE chain on L5, the rest on L3. Surface routes do not fit: no JS1 HDI single-ended structure’s clearance fits between the Micron’s 0.8 mm by 0.65 mm balls, and L3 alone does not hold every route. UG863 asks for a byte lane on one layer; this proof splits it.

• Each end drops through stacked JS1 microvias in the ball’s pad, attached to the ball’s port with PortAttachment: two per end to L3, four to L5. That is 4 or 8 vias per signal, and 12 on the CKE chain, against UG863’s budget of 2 per data, strobe, address or clock signal and 3 per CKE (“Physical Design Rules for LPDDR4/4x Signals”).

• The routes are not length matched, so some skews miss their targets.

• The JS1 vias carry no delay model: JITX uses a placeholder for each and lists that as an issue, so every routed group reads NOT MET whatever its skew. The measured delays also leave out the VP1002 package delay.

Run the issue report as main shows, importing these designs instead.

SLOT = ByteSlot(channel=<Channel.B: 'B'>, bank=2, dqs_nibble=6)

third bank (702), DQS on N6, DMI on N7.

Type:

Byte slot 3

DQ_ORDER = (5, 2, 7, 0, 3, 6, 1, 4)

a bit swap.

Type:

Memory DQ bit routed to each pin of SLOT.dq in turn

ILLEGAL_PIN = Pos(bank=1, nibble=2, pin=4)

not allowed for a channel B bit.

Type:

A DQ pin of byte slot 0 (channel A)

L3 = 2

Layer indices of the first two stripline layers.

L5 = 4

Layer indices of the first two stripline layers.

CKE_LAYER = 4

Layer of the channel B CKE chain.

L5_BITS = frozenset({3, 7})

Memory DQ bits routed on L5 with DQS; the rest of the set runs on L3.

class JS4ProofCircuit

Bases: JS4Circuit

JS4Circuit plus the legal proof routes.

illegal = False

proof_vias: list[Via]

proof_attachments: list[PortAttachment]

proof_routes: list[Route]

proof_ends()

FPGA pin, memory pin and layer of each proof route.

Return type:

list[tuple[Port, Port, int]]

class JS4IllegalProofCircuit(*args, **kwargs)

Bases: JS4ProofCircuit

The proof routes with one DQ bit sent to a channel A pin.

illegal = True

class JS4ProofDesign(*args, **kwargs)

Bases: Design

Legal assignment, code-routed.

board: Board = HDIBoard()

substrate: Substrate = HDISubstrate()

circuit: Circuit = JS4ProofCircuit()

class JS4IllegalDesign(*args, **kwargs)

Bases: Design

Illegal assignment, code-routed: the route is rejected.

board: Board = HDIBoard()

substrate: Substrate = HDISubstrate()

circuit: Circuit = JS4IllegalProofCircuit()