MT40A1G16TB_062E_F module

Micron MT40A1G16TB-062E:F DDR4 SDRAM.

16 Gb, x16, in a 96-ball split FBGA at 0.8 mm pitch.

The pin map and landpattern were carried over from JITx-Inc/jitx-protocols-ext (commit 33501cb, examples/protocols/memory/MT40A1G16TB_062E_F.py), itself a translation of the JITX Stanza model MT40A1G16TB-062E-F.stanza. They have not been rechecked against the Micron datasheet in this port; check the ball map against the datasheet before ordering a board.

jitxexamples.protocols.memory.ddr4_example connects this part to a DDR4 controller.

class SplitBGABase(num_rows=16, half_cols=3, ball_diameter=0.42, pitch=0.8, gap=3.2)

Bases: GridPlannerMixin, GridPadShapeGeneratorMixin, GridLandpatternGenerator

Split BGA: two three-column halves separated by a gap.

Parameters:

• num_rows (int)

• half_cols (int)

• ball_diameter (float)

• pitch (float)

• gap (float)

class SplitBGADecorated(*args, **kwargs)

Bases: SilkscreenOutline, Pad1Marker, ExcessCourtyard, SplitBGABase

Split BGA with decorations

class DDR4NumberingScheme

Bases: AlphaDictNumbering

Custom numbering scheme for DDR4 split BGA.

Maps grid columns 0-2 to pad columns 1-3, and grid columns 6-8 to pad columns 7-9.

col_name(col)

Return type:

str

Parameters:

col (int)

class FBGA96

Bases: A1, DDR4NumberingScheme, SplitBGADecorated

FBGA96 split BGA landpattern.

96 balls: 16 rows x 9 columns in two 3-column halves.

• Pitch: 0.80mm, Ball diameter: 0.42mm

• Gap between halves: 3.2mm

• Package body: 7.50mm x 13.0mm x 1.1mm

• Density level C

class MT40A1G16TB_062E_F(*args, **kwargs)

Bases: Component

Micron MT40A1G16TB-062E:F DDR4 SDRAM, x16, FBGA96.

The DDR4 signals are the ddr4 bundle: an x16, single-rank DDR4 with one CK pair, one bank-group bit and two bank-address bits.

• ddr4.data.DQ[0] to [7] are DQL0 to DQL7, [8] to [15] are DQU0 to DQU7.

• ddr4.data.DQS[0] and DM_n[0] are the lower byte’s strobe and mask, DQS[1] and DM_n[1] the upper byte’s.

• ddr4.acc holds CK, CKE, A0 to A16, ACT_n, BG0, BA0 and BA1, CS_n, RESET_n, ODT, PAR and ALERT_n.

The other pins are ports of their own: TEN, NC, VDD, VSS, VDDQ, VSSQ, VPP, VREFCA and ZQ.

reference_designator_prefix: str | None = 'U'

Reference designator prefix for this component. This will be used to generate a unique reference designator for each component of the same type.

Note

This field is a required data point for matching components between builds. If this value changes (including changing from unset to set), it will be treated as a new component, even if nothing else changes.

mpn: str | None = 'MT40A1G16TB-062E:F'

Manufacturer part number for this component.

manufacturer: str | None = 'Micron'

Manufacturer for this component.

ddr4 = DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1)

DDR4 interface

TEN = Port()

NC = Port()

VDD = [Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port()]

VSS = [Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port()]

VDDQ = [Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port()]

VSSQ = [Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port()]

VPP = [Port(), Port()]

VREFCA = Port()

ZQ = Port()

landpattern = FBGA96()

symbol = BoxSymbol()

mapping = [PadMapping({DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).data.DQ[0]: FBGA96().G[2], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).data.DQ[1]: FBGA96().F[7], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).data.DQ[2]: FBGA96().H[3], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).data.DQ[3]: FBGA96().H[7], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).data.DQ[4]: FBGA96().H[2], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).data.DQ[5]: FBGA96().H[8], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).data.DQ[6]: FBGA96().J[3], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).data.DQ[7]: FBGA96().J[7], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).data.DQ[8]: FBGA96().A[3], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).data.DQ[9]: FBGA96().B[8], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).data.DQ[10]: FBGA96().C[3], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).data.DQ[11]: FBGA96().C[7], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).data.DQ[12]: FBGA96().C[2], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).data.DQ[13]: FBGA96().C[8], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).data.DQ[14]: FBGA96().D[3], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).data.DQ[15]: FBGA96().D[7], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).acc.A[0]: FBGA96().P[3], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).acc.A[1]: FBGA96().P[7], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).acc.A[2]: FBGA96().R[3], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).acc.A[3]: FBGA96().N[7], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).acc.A[4]: FBGA96().N[3], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).acc.A[5]: FBGA96().P[8], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).acc.A[6]: FBGA96().P[2], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).acc.A[7]: FBGA96().R[8], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).acc.A[8]: FBGA96().R[2], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).acc.A[9]: FBGA96().R[7], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).acc.A[10]: FBGA96().M[3], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).acc.A[11]: FBGA96().T[2], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).acc.A[12]: FBGA96().M[7], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).acc.A[13]: FBGA96().T[8], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).acc.A[14]: FBGA96().L[2], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).acc.A[15]: FBGA96().M[8], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).acc.A[16]: FBGA96().L[8], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).acc.BA[0]: FBGA96().N[2], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).acc.BA[1]: FBGA96().N[8], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).acc.BG[0]: FBGA96().M[2], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).acc.CK[0].p: FBGA96().K[7], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).acc.CK[0].n: FBGA96().K[8], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).acc.CKE[0]: FBGA96().K[2], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).acc.CS_n[0]: FBGA96().L[7], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).acc.ODT[0]: FBGA96().K[3], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).acc.ACT_n: FBGA96().L[3], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).acc.RESET_n: FBGA96().P[1], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).acc.PAR: FBGA96().T[3], Port(): FBGA96().N[9], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).acc.ALERT_n: FBGA96().P[9], Port(): FBGA96().T[7], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).data.DQS[1].p: FBGA96().B[7], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).data.DQS[1].n: FBGA96().A[7], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).data.DQS[0].p: FBGA96().G[3], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).data.DQS[0].n: FBGA96().F[3], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).data.DM_n[1]: FBGA96().E[2], DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1).data.DM_n[0]: FBGA96().E[7], Port(): FBGA96().B[3], Port(): FBGA96().B[9], Port(): FBGA96().D[1], Port(): FBGA96().G[7], Port(): FBGA96().J[1], Port(): FBGA96().J[9], Port(): FBGA96().L[1], Port(): FBGA96().L[9], Port(): FBGA96().R[1], Port(): FBGA96().T[9], Port(): FBGA96().B[2], Port(): FBGA96().E[1], Port(): FBGA96().E[9], Port(): FBGA96().G[8], Port(): FBGA96().K[1], Port(): FBGA96().K[9], Port(): FBGA96().M[9], Port(): FBGA96().N[1], Port(): FBGA96().T[1], Port(): FBGA96().A[1], Port(): FBGA96().A[9], Port(): FBGA96().C[1], Port(): FBGA96().D[9], Port(): FBGA96().F[2], Port(): FBGA96().F[8], Port(): FBGA96().G[1], Port(): FBGA96().G[9], Port(): FBGA96().J[2], Port(): FBGA96().J[8], Port(): FBGA96().A[2], Port(): FBGA96().A[8], Port(): FBGA96().C[9], Port(): FBGA96().D[2], Port(): FBGA96().D[8], Port(): FBGA96().E[3], Port(): FBGA96().E[8], Port(): FBGA96().F[1], Port(): FBGA96().H[1], Port(): FBGA96().H[9], Port(): FBGA96().B[1], Port(): FBGA96().R[9], Port(): FBGA96().M[1], Port(): FBGA96().F[9]})]