lpddr4_example module

LPDDR4 example

A fictional controller drives a Micron MT53E1G32D2FW-046 WT:B (LPDDR4X/LPDDR4) over a dual-rank x32 link (two x16 channels), constrained with LPDDR4Constraint.

• Both parts expose their LPDDR4 pins as an LPDDR4 bundle, and one ordinary net joins the two bundles. There is no >>.

• The constraint names the same two bundles, so every Topology runs from a controller pin to a memory pin.

• The board is jitx.sample.SampleDesign: two layers, with 50 ohm and 100 ohm routing structures. Those are not LPDDR4 impedance targets; a real board passes its own structures.

The example is not routed, so the issue report lists each constrained path as Unconnected Topology and carries no measurement yet. Once the board is routed, by hand or with code Routes, each constraint reports its measured skew, and group.satisfied says whether it is met. To see the report, with the project’s runtime running:

import jitx

from jitxexamples.protocols.memory.lpddr4_example import LPDDR4ExampleDesign


def main() -> None:
    with jitx.runtime as rt:
        report = rt.submit(LPDDR4ExampleDesign).issues(satisfied=True, wait=30)
        if not report.complete:
            print("report incomplete: raise wait and run again")
        for group in report.groups():
            print("met" if group.satisfied else "NOT MET", group.text)
            if len(group.issues) > 1:
                for issue in group:
                    print("   ", issue.text)


if __name__ == "__main__":
    main()

Keep the two bundles on the parts themselves. On jitx 4.6, an unrouted path that passes through a circuit’s port reports No path for signal constraint instead of Unconnected Topology, which reads like a wiring fault; the same path measures normally once routed.

class ControllerLandpattern

Bases: BGA

10 x 10 ball BGA at 0.8 mm pitch for the fictional controller.

balls()

Return the balls row by row, A1 to K10.

Return type:

list[Pad]

class ExampleLPDDR4Controller

Bases: Component

Fictional LPDDR4 controller. Not a real product.

Its LPDDR4 pins are the leaves of an x32, dual-rank bundle, assigned to balls in signal_ports() order from A1; the remaining balls are ground.

reference_designator_prefix: str | None = 'U'

Reference designator prefix for this component. This will be used to generate a unique reference designator for each component of the same type.

Note

This field is a required data point for matching components between builds. If this value changes (including changing from unset to set), it will be treated as a new component, even if nothing else changes.

mpn: str | None = 'EXAMPLE-LPDDR4-CTRL'

Manufacturer part number for this component.

manufacturer: str | None = 'Fictional'

Manufacturer for this component.

lpddr4 = LPDDR4(<LPDDR4Width.x32: 32>, <LPDDR4Rank.Rank2: 2>)

Controller LPDDR4 interface

class LPDDR4Example

Bases: Circuit

Controller to memory over x32 LPDDR4, constrained, not routed.

class LPDDR4ExampleDesign(*args, **kwargs)

Bases: SampleDesign

LPDDR4 example on the sample board and substrate.

circuit: Circuit = LPDDR4Example()