rgmii module#

class RGMII[source]#

Bases: Port

Reduced Gigabit Media Independent Interface (RGMII) see https://en.wikipedia.org/wiki/Media-independent_interface#RGMII

This bundle is structured as a py:class:jitx.common.LanePair bundle.

class Lane[source]#

Bases: Port

RGMII Lane Bundle

data = (Port(), Port(), Port(), Port())#: Data bus

clk = Port()#: Clock line

ctl = Port()#: Multiplexed enable and error signals

TX = Lane()#: Transmit Lane

RX = Lane()#: Receive Lane

class Standard(data_to_clock_delay)[source]#

Parameters:: data_to_clock_delay (Toleranced)

data_to_clock_delay: Toleranced#: This is the expected delay between data to clock.

loss = 7.5#: This is the max loss in dB for all signals.

bus_skew = Toleranced(0, 1.1e-11, 1.1e-11)#: Databus skew specification.

impedance = Toleranced(50, 7.5, 7.5)#: Impedance spec for single-ended traces.

Constraint(structure: RoutingStructure | None = None)[source]#

Parameters:

standard (Standard)
structure (RoutingStructure | None)

class Version(data_to_clock_delay)[source]#

Bases: Standard, Enum

RGMII Version

RGMII v1 requires a specific Data to Clock delay in the PCB board to meet setup and hold times.

In RGMII v2, the spec introduces an optional “Internal Delay” feature. Devices that provide this are labeled “RGMII-ID”. These devices don’t require a PCB board delay because the delay can be configured in firmware.

STD = RGMII.Standard(data_to_clock_delay=Toleranced(1.75e-09, 2.5e-10, 2.5e-10))#

ID = RGMII.Standard(data_to_clock_delay=Toleranced(0, 5e-10, 5e-10))#