main module#

JS2 reference solution: a gigabit Ethernet PHY board.

A 12 V input feeds one buck regulator, which makes 3.3 V for the PHY’s AVDDH and DVDDH. The PHY’s on-chip LDO controller makes its 1.2 V core from that rail through an external P-channel MOSFET, inside the PHY circuit. The PHY’s line pairs run to an RJ45 jack with integrated magnetics, and its LED outputs drive the jack’s two LEDs. RGMII, MIIM, RESET_N and INT_N are boundary ports of the top circuit, left for the MAC and host the board plugs into.

Build (runtime required):

jitx design build jitxexamples.jumpstart_kits.js2_circuits.main.EthernetPhyDesign
INPUT_VOLTAGE = 12.0#

Nominal input in volts. The regulator sizes its inductor from it.

REGULATOR_CURRENT = 1.82#

Output current in amperes the regulator is sized for. The board draws about 330 mA from 3.3 V (KSZ9031RNX Table 3-12, 1000BASE-T full duplex: AVDDH 66.3 mA, DVDDH 41.5 mA, and the 221 mA core through the LDO). The regulator sizes its inductor for 40% ripple at this current and asks for one rated at least this current. At 1.81 A and below it asks for 3.3 uH or more: the example catalogue holds no 6.8 or 15 uH part, and its 3.3, 4.7 and 10 uH parts are rated 0.7 A or less. At 1.82 A it asks for 2.2 uH, which the catalogue holds rated 3.3 A. 1.82 A is the smallest value, to 0.01 A, that resolves.

class EthernetPhyBoard(straps=StrapConfig(phy_address=0, mode=<Mode.RGMII_ALL: 15>, clk125_output=False, led_mode=<LedMode.SINGLE: 1>), input_voltage=12.0)[source]#

Bases: Circuit

A regulator, the PHY application circuit and an RJ45 jack with magnetics, wired through their boundary ports.

No SI constraints and no routing structures are applied to this board yet: the RGMII signals and the four MDI pairs route unconstrained. JumpStart 4 covers both.

Parameters:

  • straps (StrapConfig) – the PHY strap configuration.

  • input_voltage (float) – nominal input in volts.

vin = Power()#

Board input, nominally 12 V.

rgmii = RGMII()#

PHY RGMII, toward the MAC.

miim = MIIM()#

PHY management interface, toward the MAC.

reset_n = Port()#

PHY RESET_N, active low, toward the host. The board holds the power-on RC network; the host pulls the line low to reset the PHY and otherwise leaves it undriven (open drain).

int_n = Port()#

PHY INT_N, active low, toward the host. The board holds its pull-up.

class EthernetPhyDesign(straps=StrapConfig(phy_address=0, mode=<Mode.RGMII_ALL: 15>, clk125_output=False, led_mode=<LedMode.SINGLE: 1>), input_voltage=12.0)[source]#

Bases: SampleDesign

The board as a design.

Every passive the kit adds leaves its package open; the design states the smallest package the assembler places, 0402, once for every query.

Parameters:

  • straps (StrapConfig) – the PHY strap configuration.

  • input_voltage (float) – nominal input in volts.

resistor_defaults = ResistorQuery(case=OneOf(values=('0402', '0603', '0805', '1206')))#
capacitor_defaults = CapacitorQuery(case=OneOf(values=('0402', '0603', '0805', '1206', '1210')))#