symbols module#

Symbol partitioning and pad-mapping helpers for the VP1002 component.

The generated component (xcvp1002) stays declarative: it yields SymbolPartition records and (port, (row, col)) ball assignments; the two builders here turn those into jitxlib BoxSymbol instances and a PadMapping. Keeping the builders handwritten (and tiny) means the generated file contains data-shaped code only.

Ports are never stored in extra containers on the component — a Port may have only one home in the design tree (JITX raises “encountered multiple times” otherwise). Partitions are therefore exposed as a method that yields fresh records; tests assert symbol coverage by re-calling it.

MAX_PINS_PER_BOX = 64#

Readability cap — no symbol box gets more pins than this.

class SymbolPartition(left=(), right=(), down=())[source]#

Bases: object

Ports of one schematic box: left/right rows, optional bottom column.

Parameters:
left: tuple[Port, ...] = ()#
right: tuple[Port, ...] = ()#
down: tuple[Port, ...] = ()#
ports()[source]#
Return type:

tuple[Port, ...]

build_symbols(partitions)[source]#

Turn partitions into one BoxSymbol each (empty sides skipped).

Return type:

list[BoxSymbol]

Parameters:

partitions (Iterable[SymbolPartition])

build_pad_mapping(lp, assignments, expected_total)[source]#

Map every port to its BGA pad, reconciling the ball count.

assignments carries zero-indexed (row, col) grid coordinates as emitted by the pinout generator; VersalBGA.get_pad takes the 1-indexed ball column, so the + 1 lives here and nowhere else.

Return type:

PadMapping

Parameters: