generic_20layer module#
Generic 20-layer substrate.
Explicit-symmetry stack: 20 conductor layers about a thick core, one
generic dielectric (Dk 3.0) throughout, 0.5 oz copper on every layer,
0.8 mm core. The upper half (L1..L10) interleaves ground/signal planes
with L1 as outer ground and L10 adjacent to the core as a power plane;
L11..L20 are the explicit mirror. The substrate exposes the HDI via
families needed for top-side BGA escape via the signal_via and
gnd_via accessors so designs query the substrate instead of
mirroring tables.
- class GenericDielectric(*, name=None, thickness=None, representing=None)[source]#
Bases:
DielectricGeneric low-loss dielectric – Dk 3.0, tan delta 0.004.
- class SolderMask(*, name=None, thickness=None, representing=None)[source]#
Bases:
DielectricGeneric soldermask.
- class GenericCopper(*, name=None, thickness=None, representing=None)[source]#
Bases:
Conductor0.5 oz copper – 0.0175 mm thick.
roughnessis intentionally left unset, so no per-conductor surface-roughness boundary is generated. Set it when modelling fab-grade conductor loss (a Hammerstad ratio, or a Huray(nodule_radius_m, area_ratio)tuple).
- class Generic_Stackup[source]#
Bases:
StackupExplicit 20-conductor stack with one generic dielectric throughout.
- top_mask = SolderMask(thickness=0.0127)#
- L1_Ground1 = GenericCopper(thickness=0.0175, name='L1-Ground1')#
- d_1_2 = GenericDielectric(thickness=0.1)#
- L2_Signal1 = GenericCopper(thickness=0.0175, name='L2-Signal1')#
- d_2_3 = GenericDielectric(thickness=0.1)#
- L3_Ground2 = GenericCopper(thickness=0.0175, name='L3-Ground2')#
- d_3_4 = GenericDielectric(thickness=0.1)#
- L4_Signal2 = GenericCopper(thickness=0.0175, name='L4-Signal2')#
- d_4_5 = GenericDielectric(thickness=0.1)#
- L5_Ground3 = GenericCopper(thickness=0.0175, name='L5-Ground3')#
- d_5_6 = GenericDielectric(thickness=0.1)#
- L6_Signal3 = GenericCopper(thickness=0.0175, name='L6-Signal3')#
- d_6_7 = GenericDielectric(thickness=0.1)#
- L7_Ground4 = GenericCopper(thickness=0.0175, name='L7-Ground4')#
- d_7_8 = GenericDielectric(thickness=0.1)#
- L8_Signal4 = GenericCopper(thickness=0.0175, name='L8-Signal4')#
- d_8_9 = GenericDielectric(thickness=0.1)#
- L9_Ground5 = GenericCopper(thickness=0.0175, name='L9-Ground5')#
- d_9_10 = GenericDielectric(thickness=0.1)#
- L10_Power1 = GenericCopper(thickness=0.0175, name='L10-Power1')#
- d_center = GenericDielectric(thickness=0.8, name='Core')#
- L11_Power1 = GenericCopper(thickness=0.0175, name='L11-Power1')#
- d_11_12 = GenericDielectric(thickness=0.1)#
- L12_Ground5 = GenericCopper(thickness=0.0175, name='L12-Ground5')#
- d_12_13 = GenericDielectric(thickness=0.1)#
- L13_Signal4 = GenericCopper(thickness=0.0175, name='L13-Signal4')#
- d_13_14 = GenericDielectric(thickness=0.1)#
- L14_Ground4 = GenericCopper(thickness=0.0175, name='L14-Ground4')#
- d_14_15 = GenericDielectric(thickness=0.1)#
- L15_Signal3 = GenericCopper(thickness=0.0175, name='L15-Signal3')#
- d_15_16 = GenericDielectric(thickness=0.1)#
- L16_Ground3 = GenericCopper(thickness=0.0175, name='L16-Ground3')#
- d_16_17 = GenericDielectric(thickness=0.1)#
- L17_Signal2 = GenericCopper(thickness=0.0175, name='L17-Signal2')#
- d_17_18 = GenericDielectric(thickness=0.1)#
- L18_Ground2 = GenericCopper(thickness=0.0175, name='L18-Ground2')#
- d_18_19 = GenericDielectric(thickness=0.1)#
- L19_Signal1 = GenericCopper(thickness=0.0175, name='L19-Signal1')#
- d_19_20 = GenericDielectric(thickness=0.1)#
- L20_Ground1 = GenericCopper(thickness=0.0175, name='L20-Ground1')#
- bottom_mask = SolderMask(thickness=0.0127)#
- class Generic_FabRules[source]#
Bases:
FabricationConstraints- min_copper_width: float = 0.04#
Minimum permissible copper width. This constraint will be enforced by the engine for generated copper shapes and will take precedence over other constraints and rules, such as trace width.
- min_copper_copper_space: float = 0.05#
Minimum permissible copper-to-copper spacing. This constraint will be enforced by the engine for generated copper shapes and will take precedence over other constraints and rules, such as clearance.
- min_copper_hole_space: float = 0.05#
Minimum permissible copper-to-hole spacing. This constraint will be enforced by the engine for generated copper shapes and will take precedence over other constraints and rules, such as clearance.
- min_copper_edge_space: float = 0.15#
Minimum permissible copper-to-board-edge spacing. This constraint will be enforced by the engine for generated copper shapes and will take precedence over other constraints and rules, such as clearance.
- min_hole_to_hole: float = 0.3#
Minimum distance between two holes, such as through-hole pads or vias.
- min_silk_solder_mask_space: float = 0.05#
Minimum distance between silkscreen and soldermask features.
- class Generic_Substrate(*args, **kwargs)[source]#
Bases:
SubstrateGeneric 20-layer substrate. Truly reusable: holds materials, stackup, fab rules, and HDI vias only; design-specific tags, routing structures, and fence-via rules attach in a design subclass.
- constraints: FabricationConstraints = <jitxexamples.substrates.generic_20layer.Generic_FabRules object>#
- class uVia_L1_L2(*args, **kwargs)[source]#
Bases:
Via- start_layer: int = 0#
Starting layer for the via. Setting this to a layer index other than the top layer allows for creating buried or blind vias.
- diameter: float | ViaDiameter = 0.25#
Pad diameter of the via, in mm. Can be overridden on a per-layer basis by
diameters.
- models: Mapping[tuple[int, int], PinModel] = {(0, 1): <jitx.si.PinModel object>}#
Specifies delay and loss models for the via, used by signal integrity constraints.
Each entry defines a model for a pair of layers. Layers are specified as layer indices. Models are assumed to be symmetric, so the order of layer indices is arbitrary. It is an error to specify multiple models for the same pair of layers.
It is recommended to not specify models with the same start and end layer. They will currently be ignored by the constraint solver (since path does not travel through the via) but this behavior may change in a future version of JITX. The models are given in terms of the same
jitx.si.PinModelobject used by components.>>> class MyVia(Via): >>> # Other via parameters... >>> models = { >>> # Top to bottom layer (through-hole via) >>> (0, -1): PinModel(5e-12, 0.05), >>> # Top to inner layer 1 (blind via) >>> (0, 1): PinModel(2e-12, 0.02), >>> # Inner layer 1 to inner layer 2 (buried via) >>> (1, 2): PinModel(2e-12, 0.02), >>> }
Not all layer pairs need to be specified. If you know that, for example, all usages of a via will go between the top and bottom of the board, then only that model needs to be provided.
Via models can also be generated programmatically using loops. For example, to define models for all layer pairs in a multi-layer board where delay and loss scale linearly with the number of layers traversed:
>>> class MultiModelVia(Via): >>> # Other via parameters... >>> >>> # Generate models for all layer pairs >>> total_layers = 4 >>> models = {} >>> for i in range(total_layers): >>> for j in range(i + 1, total_layers): >>> # Model that scales with number of layers >>> n_layers = j - i >>> models[(i, j)] = PinModel( >>> 2e-12 * n_layers, >>> 0.05 * n_layers >>> )
When models are not provided for a via, placeholder models are automatically inserted. When using placeholder models (models with ideal delay and loss), any timing or loss constraints involving signals through these vias will be flagged as unsatisfied. This is because the placeholder model assumes some arbitrary transmission delay and loss values, which are not set by the user. For accurate signal integrity analysis, provide calculated, measured, or simulated via models for all layer pairs used in your design.
For maximum accuracy, it is recommended to simulate or measure each specific pair of layers rather than using a simplified linear model. The loop approach is most useful for initial designs or when detailed measurements are not yet available.
- class uVia_L1_L4(*args, **kwargs)[source]#
Bases:
Via- start_layer: int = 0#
Starting layer for the via. Setting this to a layer index other than the top layer allows for creating buried or blind vias.
- diameter: float | ViaDiameter = 0.25#
Pad diameter of the via, in mm. Can be overridden on a per-layer basis by
diameters.
- models: Mapping[tuple[int, int], PinModel] = {(0, 3): <jitx.si.PinModel object>}#
Specifies delay and loss models for the via, used by signal integrity constraints.
Each entry defines a model for a pair of layers. Layers are specified as layer indices. Models are assumed to be symmetric, so the order of layer indices is arbitrary. It is an error to specify multiple models for the same pair of layers.
It is recommended to not specify models with the same start and end layer. They will currently be ignored by the constraint solver (since path does not travel through the via) but this behavior may change in a future version of JITX. The models are given in terms of the same
jitx.si.PinModelobject used by components.>>> class MyVia(Via): >>> # Other via parameters... >>> models = { >>> # Top to bottom layer (through-hole via) >>> (0, -1): PinModel(5e-12, 0.05), >>> # Top to inner layer 1 (blind via) >>> (0, 1): PinModel(2e-12, 0.02), >>> # Inner layer 1 to inner layer 2 (buried via) >>> (1, 2): PinModel(2e-12, 0.02), >>> }
Not all layer pairs need to be specified. If you know that, for example, all usages of a via will go between the top and bottom of the board, then only that model needs to be provided.
Via models can also be generated programmatically using loops. For example, to define models for all layer pairs in a multi-layer board where delay and loss scale linearly with the number of layers traversed:
>>> class MultiModelVia(Via): >>> # Other via parameters... >>> >>> # Generate models for all layer pairs >>> total_layers = 4 >>> models = {} >>> for i in range(total_layers): >>> for j in range(i + 1, total_layers): >>> # Model that scales with number of layers >>> n_layers = j - i >>> models[(i, j)] = PinModel( >>> 2e-12 * n_layers, >>> 0.05 * n_layers >>> )
When models are not provided for a via, placeholder models are automatically inserted. When using placeholder models (models with ideal delay and loss), any timing or loss constraints involving signals through these vias will be flagged as unsatisfied. This is because the placeholder model assumes some arbitrary transmission delay and loss values, which are not set by the user. For accurate signal integrity analysis, provide calculated, measured, or simulated via models for all layer pairs used in your design.
For maximum accuracy, it is recommended to simulate or measure each specific pair of layers rather than using a simplified linear model. The loop approach is most useful for initial designs or when detailed measurements are not yet available.
- class uVia_L1_L6(*args, **kwargs)[source]#
Bases:
Via- start_layer: int = 0#
Starting layer for the via. Setting this to a layer index other than the top layer allows for creating buried or blind vias.
- diameter: float | ViaDiameter = 0.25#
Pad diameter of the via, in mm. Can be overridden on a per-layer basis by
diameters.
- models: Mapping[tuple[int, int], PinModel] = {(0, 5): <jitx.si.PinModel object>}#
Specifies delay and loss models for the via, used by signal integrity constraints.
Each entry defines a model for a pair of layers. Layers are specified as layer indices. Models are assumed to be symmetric, so the order of layer indices is arbitrary. It is an error to specify multiple models for the same pair of layers.
It is recommended to not specify models with the same start and end layer. They will currently be ignored by the constraint solver (since path does not travel through the via) but this behavior may change in a future version of JITX. The models are given in terms of the same
jitx.si.PinModelobject used by components.>>> class MyVia(Via): >>> # Other via parameters... >>> models = { >>> # Top to bottom layer (through-hole via) >>> (0, -1): PinModel(5e-12, 0.05), >>> # Top to inner layer 1 (blind via) >>> (0, 1): PinModel(2e-12, 0.02), >>> # Inner layer 1 to inner layer 2 (buried via) >>> (1, 2): PinModel(2e-12, 0.02), >>> }
Not all layer pairs need to be specified. If you know that, for example, all usages of a via will go between the top and bottom of the board, then only that model needs to be provided.
Via models can also be generated programmatically using loops. For example, to define models for all layer pairs in a multi-layer board where delay and loss scale linearly with the number of layers traversed:
>>> class MultiModelVia(Via): >>> # Other via parameters... >>> >>> # Generate models for all layer pairs >>> total_layers = 4 >>> models = {} >>> for i in range(total_layers): >>> for j in range(i + 1, total_layers): >>> # Model that scales with number of layers >>> n_layers = j - i >>> models[(i, j)] = PinModel( >>> 2e-12 * n_layers, >>> 0.05 * n_layers >>> )
When models are not provided for a via, placeholder models are automatically inserted. When using placeholder models (models with ideal delay and loss), any timing or loss constraints involving signals through these vias will be flagged as unsatisfied. This is because the placeholder model assumes some arbitrary transmission delay and loss values, which are not set by the user. For accurate signal integrity analysis, provide calculated, measured, or simulated via models for all layer pairs used in your design.
For maximum accuracy, it is recommended to simulate or measure each specific pair of layers rather than using a simplified linear model. The loop approach is most useful for initial designs or when detailed measurements are not yet available.
- class uVia_L1_L8(*args, **kwargs)[source]#
Bases:
Via- start_layer: int = 0#
Starting layer for the via. Setting this to a layer index other than the top layer allows for creating buried or blind vias.
- diameter: float | ViaDiameter = 0.25#
Pad diameter of the via, in mm. Can be overridden on a per-layer basis by
diameters.
- models: Mapping[tuple[int, int], PinModel] = {(0, 7): <jitx.si.PinModel object>}#
Specifies delay and loss models for the via, used by signal integrity constraints.
Each entry defines a model for a pair of layers. Layers are specified as layer indices. Models are assumed to be symmetric, so the order of layer indices is arbitrary. It is an error to specify multiple models for the same pair of layers.
It is recommended to not specify models with the same start and end layer. They will currently be ignored by the constraint solver (since path does not travel through the via) but this behavior may change in a future version of JITX. The models are given in terms of the same
jitx.si.PinModelobject used by components.>>> class MyVia(Via): >>> # Other via parameters... >>> models = { >>> # Top to bottom layer (through-hole via) >>> (0, -1): PinModel(5e-12, 0.05), >>> # Top to inner layer 1 (blind via) >>> (0, 1): PinModel(2e-12, 0.02), >>> # Inner layer 1 to inner layer 2 (buried via) >>> (1, 2): PinModel(2e-12, 0.02), >>> }
Not all layer pairs need to be specified. If you know that, for example, all usages of a via will go between the top and bottom of the board, then only that model needs to be provided.
Via models can also be generated programmatically using loops. For example, to define models for all layer pairs in a multi-layer board where delay and loss scale linearly with the number of layers traversed:
>>> class MultiModelVia(Via): >>> # Other via parameters... >>> >>> # Generate models for all layer pairs >>> total_layers = 4 >>> models = {} >>> for i in range(total_layers): >>> for j in range(i + 1, total_layers): >>> # Model that scales with number of layers >>> n_layers = j - i >>> models[(i, j)] = PinModel( >>> 2e-12 * n_layers, >>> 0.05 * n_layers >>> )
When models are not provided for a via, placeholder models are automatically inserted. When using placeholder models (models with ideal delay and loss), any timing or loss constraints involving signals through these vias will be flagged as unsatisfied. This is because the placeholder model assumes some arbitrary transmission delay and loss values, which are not set by the user. For accurate signal integrity analysis, provide calculated, measured, or simulated via models for all layer pairs used in your design.
For maximum accuracy, it is recommended to simulate or measure each specific pair of layers rather than using a simplified linear model. The loop approach is most useful for initial designs or when detailed measurements are not yet available.
- class uGnd_L1_L3(*args, **kwargs)[source]#
Bases:
Via- start_layer: int = 0#
Starting layer for the via. Setting this to a layer index other than the top layer allows for creating buried or blind vias.
- diameter: float | ViaDiameter = 0.25#
Pad diameter of the via, in mm. Can be overridden on a per-layer basis by
diameters.
- class uGnd_L1_L5(*args, **kwargs)[source]#
Bases:
Via- start_layer: int = 0#
Starting layer for the via. Setting this to a layer index other than the top layer allows for creating buried or blind vias.
- diameter: float | ViaDiameter = 0.25#
Pad diameter of the via, in mm. Can be overridden on a per-layer basis by
diameters.
- class uGnd_L1_L7(*args, **kwargs)[source]#
Bases:
Via- start_layer: int = 0#
Starting layer for the via. Setting this to a layer index other than the top layer allows for creating buried or blind vias.
- diameter: float | ViaDiameter = 0.25#
Pad diameter of the via, in mm. Can be overridden on a per-layer basis by
diameters.
- class uGnd_L1_L9(*args, **kwargs)[source]#
Bases:
Via- start_layer: int = 0#
Starting layer for the via. Setting this to a layer index other than the top layer allows for creating buried or blind vias.
- diameter: float | ViaDiameter = 0.25#
Pad diameter of the via, in mm. Can be overridden on a per-layer basis by
diameters.
- class uFence_L1_L3(*args, **kwargs)[source]#
Bases:
Via- start_layer: int = 0#
Starting layer for the via. Setting this to a layer index other than the top layer allows for creating buried or blind vias.
- diameter: float | ViaDiameter = 0.25#
Pad diameter of the via, in mm. Can be overridden on a per-layer basis by
diameters.
- class uFence_L3_L5(*args, **kwargs)[source]#
Bases:
Via- start_layer: int = 2#
Starting layer for the via. Setting this to a layer index other than the top layer allows for creating buried or blind vias.
- diameter: float | ViaDiameter = 0.25#
Pad diameter of the via, in mm. Can be overridden on a per-layer basis by
diameters.
- class uFence_L5_L7(*args, **kwargs)[source]#
Bases:
Via- start_layer: int = 4#
Starting layer for the via. Setting this to a layer index other than the top layer allows for creating buried or blind vias.
- diameter: float | ViaDiameter = 0.25#
Pad diameter of the via, in mm. Can be overridden on a per-layer basis by
diameters.
- class uFence_L7_L9(*args, **kwargs)[source]#
Bases:
Via- start_layer: int = 6#
Starting layer for the via. Setting this to a layer index other than the top layer allows for creating buried or blind vias.
- diameter: float | ViaDiameter = 0.25#
Pad diameter of the via, in mm. Can be overridden on a per-layer basis by
diameters.
- class uFence_L18_L20(*args, **kwargs)[source]#
Bases:
Via- start_layer: int = -3#
Starting layer for the via. Setting this to a layer index other than the top layer allows for creating buried or blind vias.
- diameter: float | ViaDiameter = 0.25#
Pad diameter of the via, in mm. Can be overridden on a per-layer basis by
diameters.
- class uFence_L16_L18(*args, **kwargs)[source]#
Bases:
Via- start_layer: int = -5#
Starting layer for the via. Setting this to a layer index other than the top layer allows for creating buried or blind vias.
- diameter: float | ViaDiameter = 0.25#
Pad diameter of the via, in mm. Can be overridden on a per-layer basis by
diameters.
- class uFence_L14_L16(*args, **kwargs)[source]#
Bases:
Via- start_layer: int = -7#
Starting layer for the via. Setting this to a layer index other than the top layer allows for creating buried or blind vias.
- diameter: float | ViaDiameter = 0.25#
Pad diameter of the via, in mm. Can be overridden on a per-layer basis by
diameters.
- class uFence_L12_L14(*args, **kwargs)[source]#
Bases:
Via- start_layer: int = -9#
Starting layer for the via. Setting this to a layer index other than the top layer allows for creating buried or blind vias.
- diameter: float | ViaDiameter = 0.25#
Pad diameter of the via, in mm. Can be overridden on a per-layer basis by
diameters.
- class TH_Via(*args, **kwargs)[source]#
Bases:
Via- start_layer: int = 0#
Starting layer for the via. Setting this to a layer index other than the top layer allows for creating buried or blind vias.
- diameter: float | ViaDiameter = 0.5#
Pad diameter of the via, in mm. Can be overridden on a per-layer basis by
diameters.
- class uStitch_L1_L9(*args, **kwargs)[source]#
Bases:
Via- start_layer: int = 0#
Starting layer for the via. Setting this to a layer index other than the top layer allows for creating buried or blind vias.
- diameter: float | ViaDiameter = 0.25#
Pad diameter of the via, in mm. Can be overridden on a per-layer basis by
diameters.
- class uStitch_L12_L20(*args, **kwargs)[source]#
Bases:
Via- start_layer: int = -9#
Starting layer for the via. Setting this to a layer index other than the top layer allows for creating buried or blind vias.
- diameter: float | ViaDiameter = 0.25#
Pad diameter of the via, in mm. Can be overridden on a per-layer basis by
diameters.
- property signal_via: dict[int, type[Via]]#
Signal-launch via class keyed by signal-layer index (1..4).