ddr4_example module

DDR4 example

A fictional controller drives a Micron MT40A1G16TB-062E:F over a single-rank x16 DDR4 link, constrained with DDR4Constraint.

• Both parts expose their DDR4 pins as a DDR4 bundle, and one ordinary net joins the two bundles. There is one memory, so the address/command bus is point to point and there is no >>.

• The constraint names the same two bundles, so every Topology runs from a controller pin to a memory pin.

• The board is jitx.sample.SampleDesign: two layers, with 50 ohm and 100 ohm routing structures. Those are not DDR4 impedance targets; a real board passes its own structures.

The example is not routed, so the issue report lists each constrained path as Unconnected Topology and carries no measurement yet. To see the report, with the project’s runtime running:

import jitx

from jitxexamples.protocols.memory.ddr4_example import DDR4ExampleDesign


def main() -> None:
    with jitx.runtime as rt:
        report = rt.submit(DDR4ExampleDesign).issues(satisfied=True, wait=30)
        if not report.complete:
            print("report incomplete: raise wait and run again")
        for group in report.groups():
            print("met" if group.satisfied else "NOT MET", group.text)
            if len(group.issues) > 1:
                for issue in group:
                    print("   ", issue.text)


if __name__ == "__main__":
    main()

class ControllerLandpattern

Bases: BGA

8 x 8 ball BGA at 0.8 mm pitch for the fictional controller.

balls()

Return the balls row by row, A1 to H8.

Return type:

list[Pad]

class ExampleDDR4Controller

Bases: Component

Fictional DDR4 controller. Not a real product.

Its DDR4 pins are the leaves of an x16, single-rank bundle with one CK pair and one bank-group bit, to match the memory, assigned to balls in signal_ports() order from A1; the remaining balls are ground.

reference_designator_prefix: str | None = 'U'

Reference designator prefix for this component. This will be used to generate a unique reference designator for each component of the same type.

Note

This field is a required data point for matching components between builds. If this value changes (including changing from unset to set), it will be treated as a new component, even if nothing else changes.

mpn: str | None = 'EXAMPLE-DDR4-CTRL'

Manufacturer part number for this component.

manufacturer: str | None = 'Fictional'

Manufacturer for this component.

ddr4 = DDR4(<DDR4Width.x16: 16>, <DDR4Rank.SingleRank: 1>, ck_count=1, bg_count=1)

Controller DDR4 interface

class DDR4Example

Bases: Circuit

Controller to memory over x16 DDR4, constrained, not routed.

class DDR4ExampleDesign(*args, **kwargs)

Bases: SampleDesign

DDR4 example on the sample board and substrate.

circuit: Circuit = DDR4Example()