fpga module#

The JS1 VP1002 with one LPDDR4X x32 interface offered on banks 702 and 701.

The offer is the rule set in pinout, layout OPTIMUM_X32_FLIPPED, built as two levels of provide:

  • Per byte slot, Slot0Bit to Slot3Bit: each of the slot’s eight DQ pins, offered with all_of. Taking eight of them in any order is rule 3, the bit swap within a byte.

  • VersalLPDDR4X, offered with one_of: four options, one per allowed byte-to-slot order (rule 4, the byte swap within a channel). Each option maps the fixed pins, the slot’s DQS and DMI, and the eight DQ ports to eight pins required from the slot.

Together they offer every byte swap and bit swap the rules allow on this layout: assignment_count() assignments. The layout’s positions are those of channel 0 on AMD’s VMK180, VCK190 and VPK120 boards, CS1 aside on the single rank VCK190 (see pinout, “Inferred from the boards”); the chosen assignment is still validated in Vivado. The jitx-pin-assignment skill covers the pattern (hierarchical provider composition).

class VP1002LPDDR4X[source]#

Bases: XCVP1002Circuit

JS1’s VP1002 circuit plus the LPDDR4X offer and its system clock.

sys_clk is the DDRMC’s differential system clock input (PG313 rule 9), on the fixed sys_clk pins of the layout. Net it to a clock source.

sys_clk = DiffPair()#
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