phy module#
KSZ9031RNX gigabit Ethernet PHY application circuit.
Section, table and figure numbers cite the KSZ9031RNX data sheet, DS00002117K,
linked from datasheet.
ANLAN206 is the Microchip application note Section 11.0 cites as the LDO
controller’s design reference; its Figure 8 is the KSZ9031RNX circuit.
The circuit runs the PHY from one 3.3 V rail, for AVDDH and DVDDH. The PHY’s
on-chip LDO controller makes the 1.2 V core (AVDDL, AVDDL_PLL and DVDDL) from it
through an external P-channel MOSFET. The circuit holds the parts the PHY needs
to run: that MOSFET and its capacitors, the 25 MHz crystal and its load
capacitors, the strap-in resistors, the LED series resistors, the ISET bias
resistor, the power-on reset network, the interrupt pull-up and the supply
decoupling. Its boundary is typed: one Power port for the 3.3 V rail,
RGMII and MIIM toward the MAC, MDI1000BaseT toward the magnetics,
one Polarized port per LED output for the LED it drives, and one port each
for RESET_N and INT_N toward the host.
The MDIO pull-up is not here: it belongs to the circuit that composes the bus. The exposed pad’s thermal vias (V and EV of Figures 13-3, 13-6 and 13-9) are left to layout.
- class KSZ9031RNXCircuit(straps=StrapConfig(phy_address=0, mode=<Mode.RGMII_ALL: 15>, clk125_output=False, led_mode=<LedMode.SINGLE: 1>))[source]#
Bases:
CircuitKSZ9031RNX with its core LDO, crystal, straps, bias, reset, interrupt pull-up and decoupling.
- Parameters:
straps (
StrapConfig) – the configuration the strap resistors latch at power-up.
- vdd_3v3 = Power()#
3.3 V supply for AVDDH and DVDDH (I/O at 3.3 V), and the source of the 1.2 V core.
- rgmii = RGMII()#
RGMII toward the MAC.
TXcarries MAC to PHY,RXPHY to MAC.
- miim = MIIM()#
Management interface. MDIO needs a pull-up in the composing circuit.
- mdi = MDI1000BaseT()#
The four line pairs, A to D, toward the magnetics.
- led1 = Polarized()#
wire it anode to
a, cathode toc.- Type:
LED driven by LED1 (pin 17)
- led2 = Polarized()#
wire it anode to
a, cathode toc.- Type:
LED driven by LED2 (pin 15)
- reset_n = Port()#
RESET_N (pin 42), active low, toward the host. The circuit holds the power-on RC network; the host may pull the line low to reset the PHY and otherwise leaves it undriven, as an open-drain output does.
- int_n = Port()#
INT_N (pin 38), active low by default, toward the host. The circuit holds its pull-up.