and_gate module#
AND gate symbol for JITX Standard Library
- class ANDGateConfig(label_config=None, height=4.0, width=None, width_to_height_ratio=1.2307692307692308, filled=True, line_width=0.15, pin_length=2, pad_name_size=0.65, num_inputs=2, pin_pitch=2, inverted=False, open_collector=None)[source]#
Bases:
LabelConfigurableConfiguration for AND gate symbols
Defines the geometric and visual parameters for AND gate symbols.
- Parameters:
- height: float = 4.0#
Gate body height
- width: float | None = None#
Gate body width (from input edge to output tip). If None, automatically computed as height * width_to_height_ratio
- width_to_height_ratio: float = 1.2307692307692308#
Width to height ratio for automatic width calculation
- filled: bool = True#
Whether to fill the gate body
- line_width: float = 0.15#
Width of the gate lines
- pin_length: int = 2#
Length of the pin extensions
- pad_name_size: float | None = 0.65#
Size of the pad name text
- num_inputs: int = 2#
Number of input pins
- pin_pitch: int = 2#
Spacing between input pins
- inverted: bool = False#
Whether to add inversion bubble (creates NAND gate)
- open_collector: OpenCollectorType | None = None#
Whether to add open-collector symbol on output pin
- class ANDGateSymbol(config=None, **kwargs)[source]#
Bases:
LabelledSymbol,GenericAND gate symbol with graphics and pins. Supports configurable number of inputs and NAND functionality.
- Parameters:
config (T | None)
- gate_body: Shape[ArcPolyline | ArcPolygon]#
- leader_pins: tuple[Shape[Polyline], ...]#
- p: dict[int, Pin]#
- config: T#
- property line_width: float#
See
line_width.
- property pin_length: float#
See
pin_length.
- property num_inputs: int#
See
num_inputs.
- property label_config: LabelConfigurable#
Configuration object that provides label configuration