xcvp1002 module

AMD Versal Premium VP1002, NFVI1369 package — GENERATED MODULE.

Generated by python -m jitxexamples.jumpstart_kits.js1_stackup_components.versal_fpga.tools.generate_pinout. DO NOT EDIT BY HAND — regenerate from the AMD package pinout file instead.

Ground truth

• xcvp1002nfvi1369pkg.txt (AMD package device pinout file, sha256 f02a21966623596a... of the newline- normalized text), downloaded from https://www.amd.com/en/developer/resources/adaptive-socs-and-fpgas/package-pinout-files/versal-package-device-pinout-files.html File header identification lines:

System Message: WARNING/2 (/home/runner/work/jitx-doc/jitx-doc/lib/jitxexamples/jumpstart_kits/js1_stackup_components/versal_fpga/xcvp1002.py:docstring of jitxexamples.jumpstart_kits.js1_stackup_components.versal_fpga.xcvp1002, line 12)

Bullet list ends without a blank line; unexpected unindent.

Device : xcvp1002nfvi1369 Date : Mon Oct 16 17:52:52 2023 * AM013 “Package Dimensions for NFVI1369” (mechanical) and

System Message: ERROR/3 (/home/runner/work/jitx-doc/jitx-doc/lib/jitxexamples/jumpstart_kits/js1_stackup_components/versal_fpga/xcvp1002.py:docstring of jitxexamples.jumpstart_kits.js1_stackup_components.versal_fpga.xcvp1002, line 15)

Unexpected indentation.

“BGA Package Design Rules” (PCB land rules), via .landpattern – cited by caption because AM013 renumbers its figures between editions; see landpattern.AM013_MECHANICAL_FIGURE for the edition and page each value was read from: https://docs.amd.com/r/en-US/am013-versal-pkg-pinout

Structure

1369 balls on a full 37x37 grid, 0.92 mm pitch. Every ball has exactly one Port: unique pin names are scalar attributes; repeated rail names (GND, VCCINT, VCCO_*, NC, …) are indexed lists ordered by (row, col). Ball coordinates are zero-indexed grid positions; the ball reference strings (“A1”) exist only in the generator.

The ordering-code suffix (speed/temperature grade) is omitted from mpn; see DS959 for full ordering information.

class XCVP1002

Bases: Component

AMD Versal Premium VP1002 FPGA in the NFVI1369 package.

mpn: str | None = 'XCVP1002-NFVI1369'

Manufacturer part number for this component.

manufacturer: str | None = 'AMD'

Manufacturer for this component.

datasheet = 'https://docs.amd.com/r/en-US/am013-versal-pkg-pinout'

reference_designator_prefix: str | None = 'U'

Reference designator prefix for this component. This will be used to generate a unique reference designator for each component of the same type.

Note

This field is a required data point for matching components between builds. If this value changes (including changing from unset to set), it will be treated as a new component, even if nothing else changes.

GTY_REFCLKN0_103 = Port()

GTY_REFCLKN1_103 = Port()

GTY_REFCLKP0_103 = Port()

GTY_REFCLKP1_103 = Port()

GTY_RXN0_103 = Port()

GTY_RXN1_103 = Port()

GTY_RXN2_103 = Port()

GTY_RXN3_103 = Port()

GTY_RXP0_103 = Port()

GTY_RXP1_103 = Port()

GTY_RXP2_103 = Port()

GTY_RXP3_103 = Port()

GTY_TXN0_103 = Port()

GTY_TXN1_103 = Port()

GTY_TXN2_103 = Port()

GTY_TXN3_103 = Port()

GTY_TXP0_103 = Port()

GTY_TXP1_103 = Port()

GTY_TXP2_103 = Port()

GTY_TXP3_103 = Port()

GTY_AVTTRCAL_RS = Port()

GTY_REFCLKN0_105 = Port()

GTY_REFCLKN1_105 = Port()

GTY_REFCLKP0_105 = Port()

GTY_REFCLKP1_105 = Port()

GTY_RREF_RS = Port()

GTY_RXN0_105 = Port()

GTY_RXN1_105 = Port()

GTY_RXN2_105 = Port()

GTY_RXN3_105 = Port()

GTY_RXP0_105 = Port()

GTY_RXP1_105 = Port()

GTY_RXP2_105 = Port()

GTY_RXP3_105 = Port()

GTY_TXN0_105 = Port()

GTY_TXN1_105 = Port()

GTY_TXN2_105 = Port()

GTY_TXN3_105 = Port()

GTY_TXP0_105 = Port()

GTY_TXP1_105 = Port()

GTY_TXP2_105 = Port()

GTY_TXP3_105 = Port()

GTM_AVTTRCAL_RN = Port()

GTM_RREF_RN = Port()

GTM_REFCLKN0_202 = Port()

GTM_REFCLKN1_202 = Port()

GTM_REFCLKP0_202 = Port()

GTM_REFCLKP1_202 = Port()

GTM_RXN0_202 = Port()

GTM_RXN1_202 = Port()

GTM_RXN2_202 = Port()

GTM_RXN3_202 = Port()

GTM_RXP0_202 = Port()

GTM_RXP1_202 = Port()

GTM_RXP2_202 = Port()

GTM_RXP3_202 = Port()

GTM_TXN0_202 = Port()

GTM_TXN1_202 = Port()

GTM_TXN2_202 = Port()

GTM_TXN3_202 = Port()

GTM_TXP0_202 = Port()

GTM_TXP1_202 = Port()

GTM_TXP2_202 = Port()

GTM_TXP3_202 = Port()

GTM_AVTTRCAL_L = Port()

GTM_REFCLKN0_203 = Port()

GTM_REFCLKN1_203 = Port()

GTM_REFCLKP0_203 = Port()

GTM_REFCLKP1_203 = Port()

GTM_RREF_L = Port()

GTM_RXN0_203 = Port()

GTM_RXN1_203 = Port()

GTM_RXN2_203 = Port()

GTM_RXN3_203 = Port()

GTM_RXP0_203 = Port()

GTM_RXP1_203 = Port()

GTM_RXP2_203 = Port()

GTM_RXP3_203 = Port()

GTM_TXN0_203 = Port()

GTM_TXN1_203 = Port()

GTM_TXN2_203 = Port()

GTM_TXN3_203 = Port()

GTM_TXP0_203 = Port()

GTM_TXP1_203 = Port()

GTM_TXP2_203 = Port()

GTM_TXP3_203 = Port()

GTM_REFCLKN0_204 = Port()

GTM_REFCLKN1_204 = Port()

GTM_REFCLKP0_204 = Port()

GTM_REFCLKP1_204 = Port()

GTM_RXN0_204 = Port()

GTM_RXN1_204 = Port()

GTM_RXN2_204 = Port()

GTM_RXN3_204 = Port()

GTM_RXP0_204 = Port()

GTM_RXP1_204 = Port()

GTM_RXP2_204 = Port()

GTM_RXP3_204 = Port()

GTM_TXN0_204 = Port()

GTM_TXN1_204 = Port()

GTM_TXN2_204 = Port()

GTM_TXN3_204 = Port()

GTM_TXP0_204 = Port()

GTM_TXP1_204 = Port()

GTM_TXP2_204 = Port()

GTM_TXP3_204 = Port()

GTM_REFCLKN0_205 = Port()

GTM_REFCLKN1_205 = Port()

GTM_REFCLKP0_205 = Port()

GTM_REFCLKP1_205 = Port()

GTM_RXN0_205 = Port()

GTM_RXN1_205 = Port()

GTM_RXN2_205 = Port()

GTM_RXN3_205 = Port()

GTM_RXP0_205 = Port()

GTM_RXP1_205 = Port()

GTM_RXP2_205 = Port()

GTM_RXP3_205 = Port()

GTM_TXN0_205 = Port()

GTM_TXN1_205 = Port()

GTM_TXN2_205 = Port()

GTM_TXN3_205 = Port()

GTM_TXP0_205 = Port()

GTM_TXP1_205 = Port()

GTM_TXP2_205 = Port()

GTM_TXP3_205 = Port()

GTM_REFCLKN0_206 = Port()

GTM_REFCLKN1_206 = Port()

GTM_REFCLKP0_206 = Port()

GTM_REFCLKP1_206 = Port()

GTM_RXN0_206 = Port()

GTM_RXN1_206 = Port()

GTM_RXN2_206 = Port()

GTM_RXN3_206 = Port()

GTM_RXP0_206 = Port()

GTM_RXP1_206 = Port()

GTM_RXP2_206 = Port()

GTM_RXP3_206 = Port()

GTM_TXN0_206 = Port()

GTM_TXN1_206 = Port()

GTM_TXN2_206 = Port()

GTM_TXN3_206 = Port()

GTM_TXP0_206 = Port()

GTM_TXP1_206 = Port()

GTM_TXP2_206 = Port()

GTM_TXP3_206 = Port()

GTM_REFCLKN0_207 = Port()

GTM_REFCLKN1_207 = Port()

GTM_REFCLKP0_207 = Port()

GTM_REFCLKP1_207 = Port()

GTM_RXN0_207 = Port()

GTM_RXN1_207 = Port()

GTM_RXN2_207 = Port()

GTM_RXN3_207 = Port()

GTM_RXP0_207 = Port()

GTM_RXP1_207 = Port()

GTM_RXP2_207 = Port()

GTM_RXP3_207 = Port()

GTM_TXN0_207 = Port()

GTM_TXN1_207 = Port()

GTM_TXN2_207 = Port()

GTM_TXN3_207 = Port()

GTM_TXP0_207 = Port()

GTM_TXP1_207 = Port()

GTM_TXP2_207 = Port()

GTM_TXP3_207 = Port()

PMC_MIO0_500 = Port()

PMC_MIO1_500 = Port()

PMC_MIO2_500 = Port()

PMC_MIO3_500 = Port()

PMC_MIO4_500 = Port()

PMC_MIO5_500 = Port()

PMC_MIO6_500 = Port()

PMC_MIO7_500 = Port()

PMC_MIO8_500 = Port()

PMC_MIO9_500 = Port()

PMC_MIO10_500 = Port()

PMC_MIO11_500 = Port()

PMC_MIO12_500 = Port()

PMC_MIO13_500 = Port()

PMC_MIO14_500 = Port()

PMC_MIO15_500 = Port()

PMC_MIO16_500 = Port()

PMC_MIO17_500 = Port()

PMC_MIO18_500 = Port()

PMC_MIO19_500 = Port()

PMC_MIO20_500 = Port()

PMC_MIO21_500 = Port()

PMC_MIO22_500 = Port()

PMC_MIO23_500 = Port()

PMC_MIO24_500 = Port()

PMC_MIO25_500 = Port()

PMC_MIO26_501 = Port()

PMC_MIO27_501 = Port()

PMC_MIO28_501 = Port()

PMC_MIO29_501 = Port()

PMC_MIO30_501 = Port()

PMC_MIO31_501 = Port()

PMC_MIO32_501 = Port()

PMC_MIO33_501 = Port()

PMC_MIO34_501 = Port()

PMC_MIO35_501 = Port()

PMC_MIO36_501 = Port()

PMC_MIO37_501 = Port()

PMC_MIO38_501 = Port()

PMC_MIO39_501 = Port()

PMC_MIO40_501 = Port()

PMC_MIO41_501 = Port()

PMC_MIO42_501 = Port()

PMC_MIO43_501 = Port()

PMC_MIO44_501 = Port()

PMC_MIO45_501 = Port()

PMC_MIO46_501 = Port()

PMC_MIO47_501 = Port()

PMC_MIO48_501 = Port()

PMC_MIO49_501 = Port()

PMC_MIO50_501 = Port()

PMC_MIO51_501 = Port()

LPD_MIO0_502 = Port()

LPD_MIO1_502 = Port()

LPD_MIO2_502 = Port()

LPD_MIO3_502 = Port()

LPD_MIO4_502 = Port()

LPD_MIO5_502 = Port()

LPD_MIO6_502 = Port()

LPD_MIO7_502 = Port()

LPD_MIO8_502 = Port()

LPD_MIO9_502 = Port()

LPD_MIO10_502 = Port()

LPD_MIO11_502 = Port()

LPD_MIO12_502 = Port()

LPD_MIO13_502 = Port()

LPD_MIO14_502 = Port()

LPD_MIO15_502 = Port()

LPD_MIO16_502 = Port()

LPD_MIO17_502 = Port()

LPD_MIO18_502 = Port()

LPD_MIO19_502 = Port()

LPD_MIO20_502 = Port()

LPD_MIO21_502 = Port()

LPD_MIO22_502 = Port()

LPD_MIO23_502 = Port()

LPD_MIO24_502 = Port()

LPD_MIO25_502 = Port()

DONE_503 = Port()

ERROR_OUT_503 = Port()

MODE0_503 = Port()

MODE1_503 = Port()

MODE2_503 = Port()

MODE3_503 = Port()

POR_B_503 = Port()

PUDC_B_503 = Port()

REF_CLK_503 = Port()

RTC_PADI_503 = Port()

RTC_PADO_503 = Port()

TCK_503 = Port()

TDI_503 = Port()

TDO_503 = Port()

TMS_503 = Port()

IO_L0N_XCC_N0P1_M0P1_700 = Port()

IO_L0P_XCC_N0P0_M0P0_700 = Port()

IO_L1N_N0P3_M0P3_700 = Port()

IO_L1P_N0P2_M0P2_700 = Port()

IO_L2N_N0P5_M0P5_700 = Port()

IO_L2P_N0P4_M0P4_700 = Port()

IO_L3N_XCC_N1P1_M0P7_700 = Port()

IO_L3P_XCC_N1P0_M0P6_700 = Port()

IO_L4N_N1P3_M0P9_700 = Port()

IO_L4P_N1P2_M0P8_700 = Port()

IO_L5N_N1P5_M0P11_700 = Port()

IO_L5P_N1P4_M0P10_700 = Port()

IO_L6N_GC_XCC_N2P1_M0P13_700 = Port()

IO_L6P_GC_XCC_N2P0_M0P12_700 = Port()

IO_L7N_N2P3_M0P15_700 = Port()

IO_L7P_N2P2_M0P14_700 = Port()

IO_L8N_N2P5_M0P17_700 = Port()

IO_L8P_N2P4_M0P16_700 = Port()

IO_L9N_GC_XCC_N3P1_M0P19_700 = Port()

IO_L9P_GC_XCC_N3P0_M0P18_700 = Port()

IO_L10N_N3P3_M0P21_700 = Port()

IO_L10P_N3P2_M0P20_700 = Port()

IO_L11N_N3P5_M0P23_700 = Port()

IO_L11P_N3P4_M0P22_700 = Port()

IO_L12N_GC_XCC_N4P1_M0P25_700 = Port()

IO_L12P_GC_XCC_N4P0_M0P24_700 = Port()

IO_L13N_N4P3_M0P27_700 = Port()

IO_L13P_N4P2_M0P26_700 = Port()

IO_L14N_N4P5_M0P29_700 = Port()

IO_L14P_N4P4_M0P28_700 = Port()

IO_L15N_XCC_N5P1_M0P31_700 = Port()

IO_L15P_XCC_N5P0_M0P30_700 = Port()

IO_L16N_N5P3_M0P33_700 = Port()

IO_L16P_N5P2_M0P32_700 = Port()

IO_L17N_N5P5_M0P35_700 = Port()

IO_L17P_N5P4_M0P34_700 = Port()

IO_L18N_XCC_N6P1_M0P37_700 = Port()

IO_L18P_XCC_N6P0_M0P36_700 = Port()

IO_L19N_N6P3_M0P39_700 = Port()

IO_L19P_N6P2_M0P38_700 = Port()

IO_L20N_N6P5_M0P41_700 = Port()

IO_L20P_N6P4_M0P40_700 = Port()

IO_L21N_XCC_N7P1_M0P43_700 = Port()

IO_L21P_XCC_N7P0_M0P42_700 = Port()

IO_L22N_N7P3_M0P45_700 = Port()

IO_L22P_N7P2_M0P44_700 = Port()

IO_L23N_N7P5_M0P47_700 = Port()

IO_L23P_N7P4_M0P46_700 = Port()

IO_L24N_GC_XCC_N8P1_M0P49_700 = Port()

IO_L24P_GC_XCC_N8P0_M0P48_700 = Port()

IO_L25N_N8P3_M0P51_700 = Port()

IO_L25P_N8P2_M0P50_700 = Port()

IO_L26N_N8P5_M0P53_700 = Port()

IO_L26P_N8P4_M0P52_700 = Port()

IO_VR_700 = Port()

IO_L0N_XCC_N0P1_M0P55_701 = Port()

IO_L0P_XCC_N0P0_M0P54_701 = Port()

IO_L1N_N0P3_M0P57_701 = Port()

IO_L1P_N0P2_M0P56_701 = Port()

IO_L2N_N0P5_M0P59_701 = Port()

IO_L2P_N0P4_M0P58_701 = Port()

IO_L3N_XCC_N1P1_M0P61_701 = Port()

IO_L3P_XCC_N1P0_M0P60_701 = Port()

IO_L4N_N1P3_M0P63_701 = Port()

IO_L4P_N1P2_M0P62_701 = Port()

IO_L5N_N1P5_M0P65_701 = Port()

IO_L5P_N1P4_M0P64_701 = Port()

IO_L6N_GC_XCC_N2P1_M0P67_701 = Port()

IO_L6P_GC_XCC_N2P0_M0P66_701 = Port()

IO_L7N_N2P3_M0P69_701 = Port()

IO_L7P_N2P2_M0P68_701 = Port()

IO_L8N_N2P5_M0P71_701 = Port()

IO_L8P_N2P4_M0P70_701 = Port()

IO_L9N_GC_XCC_N3P1_M0P73_701 = Port()

IO_L9P_GC_XCC_N3P0_M0P72_701 = Port()

IO_L10N_N3P3_M0P75_701 = Port()

IO_L10P_N3P2_M0P74_701 = Port()

IO_L11N_N3P5_M0P77_701 = Port()

IO_L11P_N3P4_M0P76_701 = Port()

IO_L12N_GC_XCC_N4P1_M0P79_701 = Port()

IO_L12P_GC_XCC_N4P0_M0P78_701 = Port()

IO_L13N_N4P3_M0P81_701 = Port()

IO_L13P_N4P2_M0P80_701 = Port()

IO_L14N_N4P5_M0P83_701 = Port()

IO_L14P_N4P4_M0P82_701 = Port()

IO_L15N_XCC_N5P1_M0P85_701 = Port()

IO_L15P_XCC_N5P0_M0P84_701 = Port()

IO_L16N_N5P3_M0P87_701 = Port()

IO_L16P_N5P2_M0P86_701 = Port()

IO_L17N_N5P5_M0P89_701 = Port()

IO_L17P_N5P4_M0P88_701 = Port()

IO_L18N_XCC_N6P1_M0P91_701 = Port()

IO_L18P_XCC_N6P0_M0P90_701 = Port()

IO_L19N_N6P3_M0P93_701 = Port()

IO_L19P_N6P2_M0P92_701 = Port()

IO_L20N_N6P5_M0P95_701 = Port()

IO_L20P_N6P4_M0P94_701 = Port()

IO_L21N_XCC_N7P1_M0P97_701 = Port()

IO_L21P_XCC_N7P0_M0P96_701 = Port()

IO_L22N_N7P3_M0P99_701 = Port()

IO_L22P_N7P2_M0P98_701 = Port()

IO_L23N_N7P5_M0P101_701 = Port()

IO_L23P_N7P4_M0P100_701 = Port()

IO_L24N_GC_XCC_N8P1_M0P103_701 = Port()

IO_L24P_GC_XCC_N8P0_M0P102_701 = Port()

IO_L25N_N8P3_M0P105_701 = Port()

IO_L25P_N8P2_M0P104_701 = Port()

IO_L26N_N8P5_M0P107_701 = Port()

IO_L26P_N8P4_M0P106_701 = Port()

IO_L0N_XCC_N0P1_M0P109_702 = Port()

IO_L0P_XCC_N0P0_M0P108_702 = Port()

IO_L1N_N0P3_M0P111_702 = Port()

IO_L1P_N0P2_M0P110_702 = Port()

IO_L2N_N0P5_M0P113_702 = Port()

IO_L2P_N0P4_M0P112_702 = Port()

IO_L3N_XCC_N1P1_M0P115_702 = Port()

IO_L3P_XCC_N1P0_M0P114_702 = Port()

IO_L4N_N1P3_M0P117_702 = Port()

IO_L4P_N1P2_M0P116_702 = Port()

IO_L5N_N1P5_M0P119_702 = Port()

IO_L5P_N1P4_M0P118_702 = Port()

IO_L6N_GC_XCC_N2P1_M0P121_702 = Port()

IO_L6P_GC_XCC_N2P0_M0P120_702 = Port()

IO_L7N_N2P3_M0P123_702 = Port()

IO_L7P_N2P2_M0P122_702 = Port()

IO_L8N_N2P5_M0P125_702 = Port()

IO_L8P_N2P4_M0P124_702 = Port()

IO_L9N_GC_XCC_N3P1_M0P127_702 = Port()

IO_L9P_GC_XCC_N3P0_M0P126_702 = Port()

IO_L10N_N3P3_M0P129_702 = Port()

IO_L10P_N3P2_M0P128_702 = Port()

IO_L11N_N3P5_M0P131_702 = Port()

IO_L11P_N3P4_M0P130_702 = Port()

IO_L12N_GC_XCC_N4P1_M0P133_702 = Port()

IO_L12P_GC_XCC_N4P0_M0P132_702 = Port()

IO_L13N_N4P3_M0P135_702 = Port()

IO_L13P_N4P2_M0P134_702 = Port()

IO_L14N_N4P5_M0P137_702 = Port()

IO_L14P_N4P4_M0P136_702 = Port()

IO_L15N_XCC_N5P1_M0P139_702 = Port()

IO_L15P_XCC_N5P0_M0P138_702 = Port()

IO_L16N_N5P3_M0P141_702 = Port()

IO_L16P_N5P2_M0P140_702 = Port()

IO_L17N_N5P5_M0P143_702 = Port()

IO_L17P_N5P4_M0P142_702 = Port()

IO_L18N_XCC_N6P1_M0P145_702 = Port()

IO_L18P_XCC_N6P0_M0P144_702 = Port()

IO_L19N_N6P3_M0P147_702 = Port()

IO_L19P_N6P2_M0P146_702 = Port()

IO_L20N_N6P5_M0P149_702 = Port()

IO_L20P_N6P4_M0P148_702 = Port()

IO_L21N_XCC_N7P1_M0P151_702 = Port()

IO_L21P_XCC_N7P0_M0P150_702 = Port()

IO_L22N_N7P3_M0P153_702 = Port()

IO_L22P_N7P2_M0P152_702 = Port()

IO_L23N_N7P5_M0P155_702 = Port()

IO_L23P_N7P4_M0P154_702 = Port()

IO_L24N_GC_XCC_N8P1_M0P157_702 = Port()

IO_L24P_GC_XCC_N8P0_M0P156_702 = Port()

IO_L25N_N8P3_M0P159_702 = Port()

IO_L25P_N8P2_M0P158_702 = Port()

IO_L26N_N8P5_M0P161_702 = Port()

IO_L26P_N8P4_M0P160_702 = Port()

GND_SENSE = Port()

GND_SMON = Port()

VCCAUX_SMON = Port()

VCCINT_SENSE = Port()

VCC_BATT = Port()

VCC_FUSE = Port()

VN_500 = Port()

VP_500 = Port()

VREFN_500 = Port()

VREFP_500 = Port()

GND = [Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port()]

GTM_AVCCAUX_L = [Port(), Port()]

GTM_AVCCAUX_RN = [Port(), Port()]

GTM_AVCC_L = [Port(), Port(), Port(), Port(), Port(), Port()]

GTM_AVCC_RN = [Port(), Port(), Port()]

GTM_AVTT_L = [Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port()]

GTM_AVTT_RN = [Port(), Port(), Port(), Port()]

GTY_AVCCAUX_RS = [Port(), Port()]

GTY_AVCC_RS = [Port(), Port()]

GTY_AVTT_RS = [Port(), Port(), Port(), Port()]

NC = [Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port()]

RSVDGND = [Port(), Port()]

VCCAUX = [Port(), Port(), Port(), Port(), Port(), Port()]

VCCAUX_PMC = [Port(), Port()]

VCCINT = [Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port()]

VCCINT_GT_L = [Port(), Port(), Port(), Port(), Port()]

VCCINT_GT_R = [Port(), Port(), Port()]

VCCO_500 = [Port(), Port()]

VCCO_501 = [Port(), Port()]

VCCO_502 = [Port(), Port()]

VCCO_503 = [Port(), Port()]

VCCO_700 = [Port(), Port(), Port()]

VCCO_701 = [Port(), Port(), Port()]

VCCO_702 = [Port(), Port(), Port()]

VCC_IO = [Port(), Port()]

VCC_PMC = [Port(), Port(), Port()]

VCC_PSFP = [Port(), Port(), Port(), Port()]

VCC_PSLP = [Port(), Port(), Port()]

VCC_RAM = [Port(), Port(), Port(), Port(), Port(), Port()]

VCC_SOC = [Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port(), Port()]

landpattern = VersalBGA(num_rows=37, num_cols=37, pitch=0.92, ball_diameter=0.51).pad_config(SMDPadConfig(copper=Ellipsis, soldermask=Ellipsis, paste=Ellipsis)).package_body(RectanglePackage(height=Toleranced(3.63, 0.2, 0.2), width=Toleranced(35, 0, 0), length=Toleranced(35, 0, 0)))

ball_assignments()

Yield every (port, zero-indexed grid coordinate) pair.

Return type:

Iterator[tuple[Port, tuple[int, int]]]

gtm_quad_pins()

Structural lane/refclk pins of each GTM bank.

Return type:

dict[int, GTMQuadPins]

symbol_partitions()

Yield the schematic box partitions (see .symbols).

Return type:

Iterator[SymbolPartition]

Device

alias of XCVP1002