jitx.sample package#

The sample package contains sample classes of common base design elements, primarily useful for creating test cases, and can be used when experimenting without wanting to select a stackup or fabrication rules. The implementations in here do not reflect any real world applications, and may be changed at any time without notice, and thus should not be relied upon when creating actual designs.

>>> class MyPlayground(SampleDesign):
...     @inline
...     class circuit(Circuit):
...         silly_port = Port()
...         ...
class SoldermaskLayer(*, name=None, thickness=None)[source]#

Bases: Dielectric

Parameters:

  • name (str | None)

  • thickness (float | None)

class Core(*, name=None, thickness=None)[source]#

Bases: Dielectric

Parameters:

  • name (str | None)

  • thickness (float | None)

class Prepreg(*, name=None, thickness=None)[source]#

Bases: Dielectric

Parameters:

  • name (str | None)

  • thickness (float | None)

class Copper(*, name=None, thickness=None)[source]#

Bases: Conductor

Parameters:

  • name (str | None)

  • thickness (float | None)

class SampleStackup(layer_count)[source]#

Bases: Stackup

Parameters:

layer_count (int)

top_surface = <jitx.sample.SoldermaskLayer object>#
bottom_surface = <jitx.sample.SoldermaskLayer object>#
layers: list[Material]#
class SampleTwoLayerStackup[source]#

Bases: SampleStackup

class SampleFabConstraints[source]#

Bases: FabricationConstraints

min_copper_width: float = 0.127#

Minimum permissible copper width. This constraint will be enforced by the engine for generated copper shapes and will take precedence over other constraints and rules, such as trace width.

min_copper_copper_space: float = 0.127#

Minimum permissible copper-to-copper spacing. This constraint will be enforced by the engine for generated copper shapes and will take precedence over other constraints and rules, such as clearance.

min_copper_hole_space: float = 0.2032#

Minimum permissible copper-to-hole spacing. This constraint will be enforced by the engine for generated copper shapes and will take precedence over other constraints and rules, such as clearance.

min_copper_edge_space: float = 0.5#

Minimum permissible copper-to-board-edge spacing. This constraint will be enforced by the engine for generated copper shapes and will take precedence over other constraints and rules, such as clearance.

min_annular_ring: float = 0.1524#

Minimum annular ring around a hole or via.

min_drill_diameter: float = 0.254#

Minimum diameter of a hole either in a pad or a via.

min_silkscreen_width: float = 0.127#

Minimum width of silkscreen.

min_pitch_leaded: float = 0.35#

Minimum distance between pad centers for leaded packages.

min_pitch_bga: float = 0.35#

Minimum distance between pad centers for BGA packages.

max_board_width: float = 456.2#

Maximum width of a board.

max_board_height: float = 609.6#

Maximum height of a board.

min_silk_solder_mask_space: float = 0.15#

Minimum distance between silkscreen and soldermask features.

min_silkscreen_text_height: float = 1.0#

Minimum height of silkscreen text.

solder_mask_registration: float = 0.15#

Minimum distance between soldermask and the edge of a copper pad.

min_soldermask_opening: float = 0.152#

Minimum size of a soldermask opening shape.

min_soldermask_bridge: float = 0.102#

Minimum distance between two soldermask features.

min_th_pad_expand_outer: float = 0.1#

Minimum through-hole pad expansion on outer layers.

min_hole_to_hole: float = 0.254#

Minimum distance between two holes, such as through-hole pads or vias.

min_pth_pin_solder_clearance: float = 3.0#

Minimum distance from the outer edge of a through-hole pad to the soldermask.

class SampleSubstrate(*args, **kwargs)[source]#

Bases: Substrate

Sample substrate using a two layer stackup and the sample fabrication constraints.

stackup: Stackup = <jitx.sample.SampleTwoLayerStackup object>#
constraints: FabricationConstraints = <jitx.sample.SampleFabConstraints object>#
class MicroVia[source]#

Bases: Via

start_layer: ClassVar[int] = 0#

Starting layer for the via. Setting this to a layer index other than the top layer allows for creating buried or blind vias.

stop_layer: ClassVar[int] = 1#

Ending layer for the via.

diameter: ClassVar[float | ViaDiameter] = 0.3#

Pad diameter of the via, in mm. Can be overridden on a per-layer basis by diameters.

hole_diameter: ClassVar[float] = 0.1#

Drilled or laser-cut hole diameter for the via, in mm.

filled: ClassVar[bool] = True#

Whether the via is filled.

tented: ClassVar[set[Side] | Side | None | bool] = 0#

Whether the via is tented on Top, Bottom, or both sides. Untented sides will have a solder mask opening.

type: ClassVar[ViaType] = 2#

MechanicalDrill or LaserDrill.

Type:

Type of via drilling method

class THVia[source]#

Bases: Via

start_layer: ClassVar[int] = 0#

Starting layer for the via. Setting this to a layer index other than the top layer allows for creating buried or blind vias.

stop_layer: ClassVar[int] = -1#

Ending layer for the via.

diameter: ClassVar[float | ViaDiameter] = 0.45#

Pad diameter of the via, in mm. Can be overridden on a per-layer basis by diameters.

hole_diameter: ClassVar[float] = 0.3#

Drilled or laser-cut hole diameter for the via, in mm.

type: ClassVar[ViaType] = 1#

MechanicalDrill or LaserDrill.

Type:

Type of via drilling method

RS_50 = RoutingStructure(impedance=50 Ω)#
DRS_100 = DifferentialRoutingStructure(name=100 Ohm Differential Routing Structure, impedance=100 Ω)#

Bases: Composite

Parameters:

transform (T | None)

class SampleBoard[source]#

Bases: Board

50 x 50mm rectangle board with rounded corners.

shape: Shape = ArcPolygon(elements=(Arc(center=(20.0, 20.0), radius=5, start=0.0, arc=90.0), Arc(center=(-20.0, 20.0), radius=5, start=90.0, arc=90.0), Arc(center=(-20.0, -20.0), radius=5, start=180.0, arc=90.0), Arc(center=(20.0, -20.0), radius=5, start=270.0, arc=90.0)))#

The board outline shape.

class SampleDesign(*args, **kwargs)[source]#

Bases: Design

This is a base class for making sample designs, it has the sample board shape and substrate defined, but no main circuit.

substrate: Substrate = SampleSubstrate()#
board: Board = SampleBoard()#