JS2 — Circuit Construction and Circuit Optimization

On the roadmap — not yet available.

Picks up the Versal Premium FPGA built in JS1 and carries one GTM transceiver quad from silicon to the board edge: escaping ten differential pairs out of a 1,369-ball, 0.92 mm grid on the JS1 HDI stackup, then landing them on a high-speed connector. Construction builds the escape and lane circuits in code; optimization tunes the launch — antipads, via fences, deskew — against full-wave simulation. Follows JS1.