bga_escape module#

BGA escape-port design.

Top-level circuit + design for an HDI BGA fanout experiment. Each signal row-pair on the BGA gets a per-lane EscapeLane child Circuit that owns the lane-local geometric features: signal-via antipad KeepOut list, deskew OverlappableCopper pair, and the deskew- antipad KeepOut. Every cross-lane JITX object — diff-pair Net, signal-via and pair/insertion-control PortAttachment``s, ``PairPoint / PairInsertion / Route triple, the deskew-copper VirtualConnection``s, and the upper-reference and deskew fence ``Pour``s — is constructed and owned by ``BGALink, since JITX requires each Net / PortAttachment / Pour to live on the common ancestor of every Port it touches and the BGA Component sits at BGALink level. The diff pairs carry the 85 ohm differential routing structure via a tag rule (StriplineDiffPairTag) rather than an explicit >> topology, so no far-end terminal component is needed.

The design-specific code is split by concern across this package: design-rule tags and the antipad fence-via design_constraint rules in constraints, the substrate specialization (BGAEscapeSubstrate with its routing structures and launch profiles, anchoring those rules) in substrate, and per-lane geometry constants and helpers — including the HFSS-instrumented-lane override — in si_geometry. This file owns the per-lane EscapeLane and top-level BGALink circuit assembly plus the buildable bga_optimization_design entry point.

class EscapeLane(*, p_pad: tuple[float, float], n_pad: tuple[float, float], spec: PerSignalLayerSpec, theta_exit_deg: float, right_r_wrap: float, is_instrumented: bool = False)[source]#

Bases: Circuit

One BGA escape lane.

Owns the lane-local geometric features: signal-via antipad KeepOut list, deskew OverlappableCopper pair, and the deskew-antipad KeepOut. These have no port references and live cleanly inside this child Circuit.

Every other JITX object that touches a lane — the diff-pair Net, the signal-via and pair/insertion-control PortAttachment``s, the ``PairPoint / PairInsertion / Route triple, and the upper-reference / deskew fence Pour``s — is constructed and owned by ``BGALink. JITX’s structural rules require these objects to live on the common ancestor of every Port they touch (BGALink for objects that reference the BGA’s diff-pair Ports; the Net’s owner for Pours), and control / route elements turn out not to be valid inside a non-net-owning child Circuit either.

Each lane exposes the data BGALink needs (p_pad, n_pad, spec, signal_via_fence_shape, deskew_fence_pour_shape, deskew_left_exit, deskew_right_exit) — plain Python values that JITX does not walk as structural children.

Built from the lane’s signal-via pad coordinates, the per-signal- layer launch spec, and the deskew-arc parameters (caller derives these from deskew_knobs(lane_index)). The instrumented- lane override (mirrored L1 D-cuts plus enlarged L2/L3 circular cuts) is enabled by is_instrumented.

Parameters:

Bases: Circuit

BGA row-pair escape wiring.

Each signal row-pair gets a per-lane EscapeLane child Circuit that owns its lane-local objects (antipad keepouts, deskew copper + antipad keepout, PairPoint, PairInsertion, Route).

JITX’s structural rule — every Net / PortAttachment / Pour must live on an ancestor of every Port it references, and a Pour lives with the Net it belongs to — forces the cross-lane objects (diff-pair Nets, signal-via PortAttachments, pair/insertion-control PortAttachments, the upper-reference / deskew fence Pours, and the board-wide GND Net) onto this Circuit, the common ancestor of the BGA Component and every lane.

A tag rule applies the 85 ohm differential routing structure to every StriplineDiffPairTag net, so no >> topology or far- end terminal component is needed.

class bga_optimization_design(*args, **kwargs)[source]#

Bases: SampleDesign

substrate: Substrate = BGAEscapeSubstrate()#
circuit: Circuit = BGALink()#