serial module#

A collection of serial communication protocols

class I2C[source]#

Bases: Port

Inter-Integrated Circuit (I2C) - Serial Communication Protocol

see https://en.wikipedia.org/wiki/I%C2%B2C

sda = Port()#: Synchronous Data Line

scl = Port()#: Synchronous Clock Line

class SMBus(*, alert=False, sus=False)[source]#

Bases: Port

System Management Bus (SMBus) - Serial Communication Protocol

see http://smbus.org/specs/

Parameters:

alert (bool)
sus (bool)

smbclk = Port()#: Synchronous Clock Line

smbdat = Port()#: Synchronous Data Line

smbalert: Port | None = None#: SMBus Alert# Line

smbsus: Port | None = None#: SMBus Suspend# Line

class SPI(*, cs=False, copi=True, cipo=True)[source]#

Bases: Port

Serial Peripheral Interface (SPI) - Serial Communication Protocol

see https://en.wikipedia.org/wiki/Serial_Peripheral_Interface

Parameters:

cs (Port | None)
copi (Port | None)
cipo (Port | None)

sck = Port()#: Synchronous Clock Line

cs: Port | None = None#: Chip Select

copi: Port | None = None#: Controller Out Peripheral In

cipo: Port | None = None#: Controller In Peripheral Out

class WideSPI(width, *, cs=False)[source]#

Bases: SPI

Wide SPI Bundle with configurable data bus width

Parameters:

width (int)
cs (bool)

sck = Port()#: Synchronous Clock Line

cs: Port | None = None#: Chip Select

data: Sequence[Port]#: Data Bus

classmethod dual(cs=False)[source]#

Parameters:: cs (bool)

classmethod quad(cs=False)[source]#

Parameters:: cs (bool)

classmethod octal(cs=False)[source]#

Parameters:: cs (bool)

class OctalSPIwDQS[source]#

Bases: WideSPI

dqs = Port()#: Data strobe

class CANPhysical[source]#

Bases: Port

CAN Physical Layer Bundle

This bundle defines the physical layer for the CAN interface which consists of a differential pair H / L

H = Port()#: High side of differential pair

L = Port()#: Low side of differential pair

class CANLogical[source]#

Bases: Port

CAN Logical Interface Bundle

This interface from a microcontroller to the PHY is typically a two wire interface consisting of a TX and RX line.

rx = Port()#: Receive line

tx = Port()#: Transmit line

class UART(*, tx=True, rx=True, cts=False, rts=False, dtr=False, dsr=False, dcd=False, ri=False, ck=False, de=False)[source]#

Bases: Port

Universal Asynchronous Receiver/Transmitter (UART) Bundle

see https://en.wikipedia.org/wiki/Universal_asynchronous_receiver-transmitter

Parameters:

tx (Port | None)
rx (Port | None)
cts (Port | None)
rts (Port | None)
dtr (Port | None)
dsr (Port | None)
dcd (Port | None)
ri (Port | None)
ck (Port | None)
de (Port | None)

tx: Port | None = None#: Transmit Data Line (enabled by default)

rx: Port | None = None#: Receive Data Line (enabled by default)

cts: Port | None = None#: Clear to Send Line

rts: Port | None = None#: Ready to Send Line

dtr: Port | None = None#: Data Terminal Ready Line

dsr: Port | None = None#: Data Set Ready Line

dcd: Port | None = None#: Data Carrier Detect Line

ri: Port | None = None#: Ring Indicator Line

ck: Port | None = None#: Clock Line

de: Port | None = None#: Driver Enable Line

classmethod minimal()[source]#: Minimal UART Bundle - TX and RX only

classmethod flowcontrol()[source]#: UART with RTS/CTS flow control

class I2S[source]#

Bases: Port

Inter-Integrated Sound (I2S) Bundle - Serial Audio Interface

see https://www.nxp.com/docs/en/user-manual/UM11732.pdf

sck = Port()#: Serial Interface Clock

ws = Port()#: Word Select (Left/Right indicator)

sd = Port()#: Serial Data Signal

class Microwire(*, cs=False, do=False, di=False)[source]#

Bases: Port

Microwire serial communication protocol - subset of SPI

Parameters:

cs (Port | None)
do (Port | None)
di (Port | None)

clk = Port()#: Synchronous Clock

cs: Port | None = None#: Chip Select

do: Port | None = None#: Data Output

di: Port | None = None#: Data Input

classmethod four()[source]#: 4-wire Microwire variant - CS, DO, DI

classmethod three()[source]#: 3-wire Microwire variant - CS and DO (bidirectional data)

class JTAG[source]#

Bases: Port

JTAG Serial Interface Bundle

Typically used for debugging/testing integrated circuits.

This bundle does not include TRSTN or Target Reset. Use a separate reset bundle to provide that interface on a connector or microcontroller.

tck = Port()#: Synchronous Clock Line

tdi = Port()#: Data Input Line

tdo = Port()#: Data Output Line

tms = Port()#: State Select Line

class SWD(swo=False)[source]#

Bases: Port

Serial Wire Debug Bundle

Parameters:: swo (Port | None)

swdio = Port()#: Serial Wire Debug Data I/O Line

swdclk = Port()#: Serial Wire Debug Clock Line

swo: Port | None = None#: Serial Wire Output Line