circuit module#

XCVP1002 wrapped with the circuit boundary a board designer consumes.

Pattern

The standard JITX FPGA-wrapper shape: one Power port per supply rail, named power nets, distinct ground domains, and GT transceiver quads exposed as bundle ports wired through the >> topology operator.

One deliberate discipline: wrapper code in the wild often resolves component pins with getattr name composition (f"GTM_TXP{lane}_{bank}"); this repo’s conventions forbid reflection, so the wiring here consumes the generated structural gtm_quad_pins() groupings instead — every pin reference is an explicit attribute.

Scope (JS1 · Part 3)

Power/ground and the six GTM quads only. XPIO / PS-MIO bank bundles, GPIO mass-Provide pin assignment, and per-net via fanout are board- level concerns deferred to JS2. Unwrapped pins remain reachable via self.fpga.

Ground domains (three, kept distinct)

  • main GND — all 689 GND balls, both RSVDGND balls, and every main rail’s Vn.

  • GND_SMON — the system-monitor analog ground: pwr_vccaux_smon.Vn and the GND_SMON ball only.

  • GND_SENSE — the VCCINT Kelvin sense return: pwr_vccint_sense.Vn and the GND_SENSE ball only.

Rail roster

XCVP1002Circuit.rail_ties() — taken verbatim from the generated component’s rail inventory (the AMD pinout file is the ground truth); no rail invented, none dropped. The roster is a method returning fresh records because a Port may have only one home in the design tree.

class GroundDomain(*values)[source]#

Bases: Enum

MAIN = 'GND'#
SMON = 'GND_SMON'#
SENSE = 'GND_SENSE'#
class RailTie(label, port, pins, domain=GroundDomain.MAIN)[source]#

Bases: object

One supply rail: boundary port, component pins, ground domain.

Parameters:
label: str#
port: Power#
pins: tuple[Port, ...]#
domain: GroundDomain = 'GND'#
class XCVP1002Circuit[source]#

Bases: Circuit

VP1002 with power/ground and GTM transceiver boundary ports.

pwr_vccint = Power()#
pwr_vcc_soc = Power()#
pwr_vccaux = Power()#
pwr_vcc_ram = Power()#
pwr_vcc_io = Power()#
pwr_vcc_psfp = Power()#
pwr_vcc_pslp = Power()#
pwr_vcc_pmc = Power()#
pwr_vccaux_pmc = Power()#
pwr_vcco_500 = Power()#
pwr_vcco_501 = Power()#
pwr_vcco_502 = Power()#
pwr_vcco_503 = Power()#
pwr_vcco_700 = Power()#
pwr_vcco_701 = Power()#
pwr_vcco_702 = Power()#
pwr_gtm_avcc_l = Power()#
pwr_gtm_avcc_rn = Power()#
pwr_gtm_avccaux_l = Power()#
pwr_gtm_avccaux_rn = Power()#
pwr_gtm_avtt_l = Power()#
pwr_gtm_avtt_rn = Power()#
pwr_gty_avcc_rs = Power()#
pwr_gty_avccaux_rs = Power()#
pwr_gty_avtt_rs = Power()#
pwr_vccint_gt_l = Power()#
pwr_vccint_gt_r = Power()#
pwr_vcc_batt = Power()#
pwr_vcc_fuse = Power()#
pwr_vccaux_smon = Power()#
pwr_vccint_sense = Power()#
VP_500 = Port()#
VN_500 = Port()#
VREFP_500 = Port()#
VREFN_500 = Port()#
GTM_AVTTRCAL_L = Port()#
GTM_RREF_L = Port()#
GTM_AVTTRCAL_RN = Port()#
GTM_RREF_RN = Port()#
GTY_AVTTRCAL_RS = Port()#
GTY_RREF_RS = Port()#
rail_ties()[source]#

The full supply-rail roster, fresh records each call.

Return type:

list[RailTie]

gtm: dict[int, GTMQuad]#
rail_nets: list[Net]#