bundles module#

Port bundles for the Versal side of an LPDDR4X x32 interface.

The memory side is LPDDR4. The Versal DDRMC drives one CKE per channel, where a dual-rank memory has one per rank (see “Inferred from the boards” in pinout), so the controller side is LPDDR4SharedCKE and the design nets its one CKE to both memory CKE balls.

class VersalLPDDR4X[source]#

Bases: LPDDR4SharedCKE

An x32 LPDDR4X interface of a Versal DDRMC: channels A (DQ0 to DQ15) and B (DQ16 to DQ31), and the memory reset.

reset_n = Port()#: Memory reset, active low

class Slot0Bit[source]#

Bases: Port

One DQ pin of byte slot 0. See fpga.VP1002LPDDR4X.

p = Port()#

class Slot1Bit[source]#

Bases: Port

One DQ pin of byte slot 1.

p = Port()#

class Slot2Bit[source]#

Bases: Port

One DQ pin of byte slot 2.

p = Port()#

class Slot3Bit[source]#

Bases: Port

One DQ pin of byte slot 3.

p = Port()#

SLOT_BITS: tuple[type[Slot0Bit | Slot1Bit | Slot2Bit | Slot3Bit], ...] = (<class 'jitxexamples.jumpstart_kits.js4_fpga_lpddr4x.bundles.Slot0Bit'>, <class 'jitxexamples.jumpstart_kits.js4_fpga_lpddr4x.bundles.Slot1Bit'>, <class 'jitxexamples.jumpstart_kits.js4_fpga_lpddr4x.bundles.Slot2Bit'>, <class 'jitxexamples.jumpstart_kits.js4_fpga_lpddr4x.bundles.Slot3Bit'>)#: The DQ pin type of each byte slot, in pinout.OPTIMUM_X32_FLIPPED order.