main module#
JS3 Part 2 reference solution: USB 2.0 from an RP2040 through a PUSB3FR4 ESD array to a USB Type-C receptacle, with the ESD channels left to pin assignment.
Parts and sources:
Raspberry Pi RP2040 (
jitxexamples.components.mcus.raspberry_pi_RP2040), the MCU side of the link, wired as a USB device, with its 27 ohm series resistors: Raspberry Pi Ltd, “RP2040 Datasheet”, build-date 2025-02-20, section 1.4.2 and Table 620. Its USB controller supports a Full Speed device (12 Mbit/s), section 1.4.2.Nexperia PUSB3FR4 (
esd.ProtectedPair): Nexperia, “PUSB3FR4 ESD protection for ultra high-speed interfaces”, Product data sheet, 12 July 2018. The channel freedom and its citations are inesd.Molex 2012670005 USB Type-C receptacle (
jitxexamples.components.connectors.molex_2012670005).USB Type-C wiring for a USB 2.0 device: Microchip AN1953, “Introduction to USB Type-C”, DS00001953A, 2015, https://ww1.microchip.com/downloads/en/Appnotes/00001953A.pdf. Section 1.3.1: the two D+ and D- contacts (A6/B6, A7/B7) are shorted on the board. Section 3.2 and Table 7: a device (UFP) pulls CC1 and CC2 down with 5.1 kOhm, at most 10% tolerance for Type-C current advertising.
The SI constraint is DiffPairConstraint with the USB 2.0 limits from
jitxlib.protocols.usb.USB.v2: skew 0 +/- 3.75 ps, insertion loss 12 dB.
They are jitxlib-standard’s generic values (usb.py cites no source), were
not checked against the USB 2.0 specification, and the skew limit is far tighter
than a Full Speed link needs (one bit is 83 ns), so the proofs show the constraint binding,
not compliance. The routing structure is JS1’s HDISubstrate.DRS_100, the
stackup’s only differential structure: USB 2.0 asks for 90 ohm +/- 15%
(USB.v2.impedance, 76.5 to 103.5 ohm) and 100 ohm falls inside it. The
constraint runs from the RP2040’s own USB pins to the connector’s A6/A7 pins,
so it covers the series resistors (each with a 0 s, 0 dB BridgingPinModel,
a modelling assumption) and the ESD channels. The B6/B7 contacts sit on the
same nets as a stub, outside the measured path.
Out of scope: power entry. VBUS and 3V3 are named nets with no
regulator between them; the kit is about the data path.
- CC_PULLDOWN = <Quantity(5100.0, 'ohm')>#
Rd, 5.1 kOhm to GND on each CC pin of a device.
- Type:
AN1953 Table 7
- CC_PULLDOWN_TOLERANCE = 0.01#
The 1% grade, inside AN1953 Table 7’s 10% limit for Type-C current advertising.