bundles module

Versal GTM transceiver bundle and its structural pin grouping.

Bundle shape

Follows the JITX Versal protocol-bundle convention: a GT quad is four LanePair lanes plus two reference-clock diff pairs. On the VP1002 in NFVI1369 each GTM bank (202-207) carries exactly 4 x (RXP/RXN + TXP/TXN) lanes and 2 x REFCLKP/REFCLKN pairs — see the per-bank rows of the AMD package pinout file (xcvp1002nfvi1369pkg.txt) and AM013 (v1.9) “GTM Transceiver Pins”.

Naming

LanePair keeps the upper-case TX/RX sub-port style of jitx.common; DiffPair uses lower-case p/n (the Python convention). Consumers therefore write quad.L[0].TX.p.

GTMQuadPins

The structural grouping the generated XCVP1002 component exposes for each GTM bank so the circuit wrapper can wire a GTMQuad bundle without composing attribute names at runtime. (Wrapper code in the wild often resolves pins via getattr name composition; this repo’s conventions forbid that — every reference in a GTMQuadPins is an explicit attribute of the generated component.)

class GTMQuad

Bases: Port

Versal GTM transceiver quad: 4 lanes + 2 reference clocks.

L: Sequence[LanePair]

REFCLK: Sequence[DiffPair]

class GTMQuadPins(rxp, rxn, txp, txn, refclkp, refclkn)

Bases: object

Component pins of one GTM bank, in lane / refclk index order.

Parameters:

• rxp (tuple[Port, ...])

• rxn (tuple[Port, ...])

• txp (tuple[Port, ...])

• txn (tuple[Port, ...])

• refclkp (tuple[Port, ...])

• refclkn (tuple[Port, ...])

rxp: tuple[Port, ...]

rxn: tuple[Port, ...]

txp: tuple[Port, ...]

txn: tuple[Port, ...]

refclkp: tuple[Port, ...]

refclkn: tuple[Port, ...]