main module#
JS4 shipping design: the VP1002 driving a Micron MT53E1G32D2FW LPDDR4X.
The FPGA offers every byte swap and bit swap AMD’s rules allow on one
layout, the single channel x32 pinout, flipped, on banks 702 and 701
(fpga), with each position where AMD’s VMK180, VCK190 and VPK120
boards put it, CS1 aside on the single rank VCK190 (pinout). The design requires one interface, nets it
to the memory with plain nets, and applies the UG863 timing constraints
(constraint). JITX picks the assignment when the board is routed.
The design has no routes, so its issue report shows each constrained path
unassigned, or for CKE without a path; proof routes part of it in
code to show the constraints bind. Vivado validation of the chosen
assignment is the designer’s step: the kit exports no XDC.
Board and substrate are JS1’s 20-layer HDI stackup on its 80 x 80 mm board.
To see the report, save this as a script in the project root and run it with the project’s runtime running:
import jitx
from jitxexamples.jumpstart_kits.js4_fpga_lpddr4x.main import JS4Design
def main() -> None:
with jitx.runtime as rt:
report = rt.submit(JS4Design).issues(satisfied=True, wait=30)
if not report.complete:
print("report incomplete: raise wait and run again")
for group in report.groups():
print("met" if group.satisfied else "NOT MET", group.text)
if len(group.issues) > 1:
for issue in group:
print(" ", issue.text)
if __name__ == "__main__":
main()
main() sits behind the __name__ guard because JITX design discovery
imports every .py file under the project root.
Not modeled yet: the system clock source, memory power rails and decoupling, CKE termination, the RESET_n pull-down, ZQ and ODT resistors, and the IO_VR_700 resistor.