Tutorial: Power circuits and power layout¶

Prerequisite

Before starting this tutorial, build the design from Tutorial: Autoroute and layout

Below is a walkthrough and companion code for ease of reading.

Resources¶

Awesome JITX – a collection of shared libraries
Starting code: JITX Project – Created from the layout tutorial
Final tutorial code – Reference designs created during this video
Board View UI Documentation

2. Write the Power Code¶

2.1 Install New Libraries¶

Add the following lines in your slm.toml file:

TI-vreg = { git = "JITx-Inc/TI-VREG", version = "0.4.0" }
power-systems = { git = "JITx-Inc/power-systems", version = "0.5.0" }

2.2 Create a New Power File¶

Create a new file, src/power.stanza, to hold your power-management module. Include core JITX imports and declare a package:

#use-added-syntax(jitx)

defpackage ethernet-io/power :
  import core
  import jitx
  import jitx/commands
  import jitx/parts

  import helpers
  import jsl

2.3 Define the Power Module and Ports¶

You will need three rails: 3.3 V, USB 5 V, and 1.2 V. In the same file, create a pcb-module with these ports:

public pcb-module power-management :
  port VDD-3v3 : power
  port VDD-USB : power
  port VDD-1v2 : power

2.4 Add a 24 V → 5.5 V Buck Regulator¶

Use the TI TPS6293x parametric circuit from TI-vreg Library. First, define constraints (input voltage range, output set point, ripple, etc.), then instantiate:

  val buck-5V-cst = power-systems/DC-DC/buck/BuckConstraints(
    v-in = min-max(20.0, 28.0),       ; Accepts ~20–28 V input
    v-out = 5.5 +/- (2 %),           ; Output ~5.5 V
    v-in-ripple-max = 0.050,         ; 50 mV input ripple
    v-out-ripple-max = 0.030,        ; 30 mV output ripple
    i-out = 1.0 +/- (20 %),          ; 1 A output
    freq = 1.2e6,                    ; Switching frequency
    K = (40 %)                       ; K-factor method for inductor sizing
  )

  inst DCDC-5V : TI-vreg/components/TPS6293x/circuit(
    TI-vreg/components/TPS6293x/TPS62932DRL,
    buck-5V-cst,
    freq = 1.2e6,
    SS-period = 10.0e-3 +/- 2.0e-3,
    UVLO = [15.0, 12.0]
  )

2.5 Add the 3.3 V Buck¶

Define constraints for the TPS6208 regulator that steps ~5.5 V down to 3.3 V:

  val cxt-3v3 = power-systems/DC-DC/buck/BuckConstraints(
    v-in = min-max(4.9, 5.5),
    v-out = 3.3 +/- (3 %),
    v-in-ripple-max = 0.050,
    v-out-ripple-max = 0.030,
    i-out = 1.0 +/- (20 %),
    freq = 1.2e6,
    K = (40 %)
  )

  inst DCDC-3v3 : TI-vreg/components/TPS6208x/circuit(
    TI-vreg/components/TPS6208x/TPS62082DSG,
    cxt-3v3,
    snooze-mode = false,
    snooze-conn? = create-resistor(
      resistance = 0.0,
      precision = (1 %)
    )
  )

2.6 Add the 1.2 V Buck¶

Similarly, define constraints for a 1.2 V rail (common as a core voltage for MCUs or PHYs):

  val cxt-1v2 = power-systems/DC-DC/buck/BuckConstraints(
    v-in = min-max(4.9, 5.5),
    v-out = 1.2 +/- (5 %),
    v-in-ripple-max = 0.050,
    v-out-ripple-max = 0.030,
    i-out = 1.0 +/- (20 %),
    freq = 1.2e6,
    K = (40 %)
  )

  inst DCDC-1v2 : TI-vreg/components/TPS6208x/circuit(
    TI-vreg/components/TPS6208x/TPS62082DSG,
    cxt-1v2,
    snooze-mode = false,
    snooze-conn? = create-resistor(
      resistance = 0.0,
      precision = (1 %)
    )
  )

2.7 Diode-OR the 5 V with USB¶

Use either USB 5 V or the buck’s 5.5 V to power the 1.2V and 3.3V regulators. The power systems library) has a parametric diode-OR function:

  inst USB-OR : power-systems/filters/diode-OR(diodes/SSA33L/component, 2)
  net (USB-OR.vin[0] VDD-USB)              ; USB supply
  net (USB-OR.vin[1] DCDC-5V.conv.VOUT)    ; 5.5 V from buck
  net (USB-OR.vout DCDC-3v3.conv.VIN DCDC-1v2.conv.VIN)

2.8 Wire Outputs to the Ports¶

Connect each regulator’s output to the appropriate port:

  net (DCDC-3v3.conv.VOUT VDD-3v3)
  net (DCDC-1v2.conv.VOUT VDD-1v2)

2.9 Enforce Power-Up Sequence¶

Require the 1.2 V rail to come up before 3.3 V:

  net (DCDC-1v2.enable USB-OR.vout.V+)
  net (DCDC-1v2.power-good DCDC-3v3.enable)
  insert-pullup(DCDC-3v3.enable USB-OR.vout)

2.10 Add a Terminal Block for 24 V Input¶

Finally, bring in a 24 V supply via a 4-pin terminal block:

  inst terminal-block : connectors/components/LSF-SMT/component(num-poles = 4)
  net P24V (terminal-block.p[1] terminal-block.p[2] DCDC-5V.conv.VIN.V+)
  net GND (terminal-block.p[3] terminal-block.p[4] DCDC-5V.conv.VIN.V- VDD-USB.V-)

3. Connect It All Together in `main`¶

With power.stanza complete, import and instantiate it in main.stanza. Then connect its ports to other modules:

BeforeAfter

#use-added-syntax(jitx)

defpackage main :
  import core
  import jitx
  import jitx/commands
  import jitx/parts

  import helpers
  import jsl

  import ethernet-io/controller      

val board-shape = RoundedRectangle(100.0, 70.0, 3.0)

pcb-module communications-core :
  port rail-3v3 : power

  inst ctl : controller

#use-added-syntax(jitx)

defpackage main :
  import core
  import jitx
  import jitx/commands
  import jitx/parts

  import helpers
  import jsl

  import ethernet-io/power            
  import ethernet-io/controller      

val board-shape = RoundedRectangle(100.0, 70.0, 3.0)

pcb-module communications-core :
  port rail-3v3 : power

  inst pwr-mng : power-management
  inst ctl : controller

  ; Example: wire your controller to the power rails
  net (pwr-mng.VDD-3v3 rail-3v3 ctl.rail-3v3)
  net (pwr-mng.VDD-USB ctl.VDD-USB)
  net (pwr-mng.VDD-1v2 ctl.VDD-1v2)

4. Route Power¶

Once your regulators are defined and instantiated, place and route them for optimal performance.

4.1 Add Vias for Ground or Layer Transitions¶

Highlight ground pads or other pads you want to via to internal planes
Press Shift + V to auto-add vias to the correct net

4.2 Create Power Pours¶

Select the pads you want to flood with copper (e.g., output of buck inductor + capacitors)
Press C to create a copper pour on the active layer
- Press Shift + C to create a pour with a configurable expansion
The net of the pour is assigned to the last pad created
As things move, the pour updates automatically to contain all the pads selected when it was created (unless shape was manually edited)

4.3 Modify Pour Shapes¶

Select the pour, press M
Drag edges/corners to reshape
Hold Shift to add new vertices
Press S to toggle free-form sculpt mode
Press Enter to finish

4.4 Set Pour Priority & Clearance¶

If overlapping pours exist (e.g., ground planes vs. local high-current pours), use rank to set priority: - Select pour and edit its rank - Adjust isolation in the same menu

5. Practical Tips¶

Use Parametric Libraries
- Leverage built-in solver functionality for power circuits
- Specify input/output voltage, ripple, current requirements
- Automate inductor, feedback, and capacitor selection
- Generators like diode-OR reduce errors
Autoroute Power
- Dynamically created pours/regions help optimize power layouts
- Region creation also works for keepouts and other layer geometry

6. Summary and Next Steps¶

You have now: 1. Written a power-management module with multiple rails. 2. Connected it to your main board. 3. Explored power layout essentials like vias, pours, shape modifications, and priorities.

Continue refining your layout for specific mechanical constraints and noise considerations. In the next tutorial, you can learn more about high-speed routing techniques and advanced layout strategies. Tutorial: High speed routing