Tutorial: Create a circuit¶

NOTE: Before starting this tutorial, you should have installed JITX and created your first design.

This document contains all code examples and product actions from Quickstart 2 in a format that's easy to follow along with. Use it as a companion to the video tutorial.

Resources¶

Shared repositories: https://github.com/JITx-Inc/awesome-jitx
Tutorial code: https://github.com/JITx-Inc/quickstart-by-phase/tree/main/quickstart-2-files

Development Tips¶

Restart terminal after modifying slm.toml
Use Ctrl+Enter to run current file
Verify package names and imports match project structure

1. Project Setup¶

Update Main Module¶

First, rename the default module in main.stanza:

# Change from:
pcb-module my-design:

# To:
pcb-module top-level:

Update the main module reference:

# Change:
set-main-module(my-design)

# To:
set-main-module(top-level)

2. Creating the Communications Core¶

Initial Module Setup¶

Create a new module in main.stanza:

pcb-module communications-core :
  ; Components will be added here

Adding Components¶

Add Zener Diode:
Open JITX sidebar
Click "Find components"
Search for "MMSZ4689T1G"

Use "Copy to clipboard"

inst zener : create-part(mpn = "MMSZ4689T1G", manufacturer = "ON Semiconductor")

Instantiate in Top Level:

pcb-module top-level :
  inst core : communications-core

3. USB Interface Integration¶

Add Library Dependency In slm.toml:

connectors = { git = "JITx-Inc/connectors", version = "0.4.1" }

Add USB Connector

inst usb-if : connectors/components/USB/USBTypeC/USBC-HighSpeed-Iface()

Connect Zener to USB Power

net (zener.A usb-if.VDD-USB.V-)
net (zener.K usb-if.VDD-USB.V+)

4. Controller Module Development¶

File Structure¶

Create src/controller.stanza:

#use-added-syntax(jitx)
defpackage ethernet-io/controller :
  import core
  import jitx
  import jitx/commands
  import jitx/parts
  import helpers
  import jsl

public pcb-module controller :
  port rail-3v3 : power
  port USB : usb-data
  port VDD-USB : power
  name = "MCU"

Project Configuration¶

Update stanza.proj:

packages ethernet-io/* defined-in "src/"

FTDI Integration¶

Add FTDI Library:

FTDI = { git = "JITx-Inc/FTDI", version = "0.3.3" }

Add Debug Interface:

inst debug-if : FTDI/DebugIF/circuit(
  FTDI/components/FT2232HL/FT2232H-MPSSE,
  FTDI/components/FT2232HL/FT2232H-RS232,
  R-query = R-query,
  C-query = C-query
)

Debug Interface Connections¶

net (rail-3v3 debug-if.VDD-3v3)
net (VDD-USB debug-if.VDD-USB)
net (USB debug-if.USB)

5. EEPROM Component Creation¶

Component Definition¶

Create src/components/MC-93LC46CT.stanza:

#use-added-syntax(jitx)
defpackage components/MC-93LC46CT:
  import core
  import jitx
  import jitx/commands
  import jitx/parts
  import jsl

public pcb-component component :
  name = "MC-93LC46CT"
  description = "1K 2.5V Microwire Serial EEPROM, SOIC-8 Package"
  mpn = "93LC46CT-I/SN"
  manufacturer = "Microchip Technology"
  datasheet = "https://ww1.microchip.com/downloads/en/DeviceDoc/20001749K.pdf"
  reference-prefix = "U"

  pin-properties:
    [pin:Ref  | pads:Int | side:Dir ]
    [CS       | 1        | Left     ] ; Chip Select
    [CLK      | 2        | Left     ] ; Serial Clock
    [DI       | 3        | Left     ] ; Data Input  
    [DO       | 4        | Left    ] ; Data Output
    [VSS      | 5        | Left     ] ; Ground
    [VCC      | 8        | Right       ] ; Power Supply
    [ORG      | 6        | Right    ] ; Memory Configuration
    [NC       | 7        | Right    ] ; No Connection

  val box = BoxSymbol(self)
  val symb = create-symbol(box)
  assign-symbol(symb)

  val pkg = SOIC-N(
    num-leads = 8,
    lead-span = min-max(5.8, 6.2),
    package-length = min-max(4.8, 5.0)
    density-level = DensityLevelA
  )
  val lp = create-landpattern(pkg)
  assign-landpattern(lp)

EEPROM Module¶

public pcb-module module :
  port VDD-3v3 : power
  port cfg : microwire-4()

  inst EEPROM : components/MC-93LC46CT/component
  net (EEPROM.CS cfg.cs)
  net (EEPROM.CLK cfg.clk)
  net (EEPROM.DO cfg.do)
  net (EEPROM.DI cfg.di)
  net (EEPROM.VCC VDD-3v3.V+)
  net (EEPROM.VSS VDD-3v3.V-)

  insert-resistor(
    EEPROM.ORG EEPROM.VCC
    helpers/R-query
    resistance = 10.e3
  )

  insert-capacitor(
    EEPROM.VCC EEPROM.VSS
    helpers/C-query
    capacitance = 2.2e-6
    short-trace? = true
  )

Integration¶

Add to controller:

inst EEPROM : components/MC-93LC46CT/module
net (EEPROM.VDD-3v3 rail-3v3)
net (EEPROM.cfg debug-if.CFG)

Key Concepts Learned¶

Component Management
Adding from database
Creating custom components
Using library code
Circuit Organization
Module hierarchy
File structure
Package management
Connectivity
Using nets
Port creation
Interface bundles
Library Usage
Adding dependencies
Importing modules
Using parametric circuits