"""AMD Versal Premium VP1002, NFVI1369 package — GENERATED MODULE.
Generated by ``python -m jitxexamples.jumpstart_kits.js1_stackup_components.versal_fpga.tools.generate_pinout``. DO NOT EDIT BY HAND —
regenerate from the AMD package pinout file instead.
Ground truth
* ``xcvp1002nfvi1369pkg.txt`` (AMD package device pinout file,
sha256 ``f02a21966623596a...`` of the newline-
normalized text), downloaded from
https://www.amd.com/en/developer/resources/adaptive-socs-and-fpgas/package-pinout-files/versal-package-device-pinout-files.html
File header identification lines::
Device : xcvp1002nfvi1369
Date : Mon Oct 16 17:52:52 2023
* AM013 "Package Dimensions for NFVI1369" (mechanical) and
"BGA Package Design Rules" (PCB land rules), via
``.landpattern`` -- cited by caption because AM013
renumbers its figures between editions; see
``landpattern.AM013_MECHANICAL_FIGURE`` for the edition
and page each value was read from:
https://docs.amd.com/r/en-US/am013-versal-pkg-pinout
Structure
1369 balls on a full 37x37 grid, 0.92 mm pitch.
Every ball has exactly one ``Port``: unique pin names are
scalar attributes; repeated rail names (GND, VCCINT, VCCO_*,
NC, ...) are indexed lists ordered by (row, col). Ball
coordinates are zero-indexed grid positions; the ball
reference strings ("A1") exist only in the generator.
The ordering-code suffix (speed/temperature grade) is omitted from
``mpn``; see DS959 for full ordering information.
"""
from collections.abc import Iterator
from dataclasses import dataclass
from enum import Enum
import jitx
from jitx.net import Port
from .bundles import GTMQuadPins
from .landpattern import NFVI1369, make_landpattern
from .symbols import SymbolPartition, build_pad_mapping, build_symbols
PINOUT_SHA256 = "f02a21966623596a7b38a5e658a2a602053e2be5342831aa6f2acda82a856b04"
TOTAL_BALLS = 1369
[docs]
class DDRMC(Enum):
"""The "DDRMC Only" column of the pin file, for an XPIO pin.
Defined in AM013 "About ASCII Package Files". NO does not exclude a
pin from DDR memory use: it means the pin also has full access to
I/O logic resources."""
YES = "YES"
"DDR memory applications only; no full access to I/O logic"
YES_PLUS_GC = "YES_PLUS_GC"
"DDR memory applications, with full access to clock management"
NO = "NO"
"Full access to I/O logic resources"
[docs]
@dataclass(frozen=True)
class TripletPin:
"""One XPIO pin of a DDRMC triplet and its DDRMC column value."""
port: Port
ddrmc: DDRMC
[docs]
class XCVP1002(jitx.Component):
"""AMD Versal Premium VP1002 FPGA in the NFVI1369 package."""
mpn = "XCVP1002-NFVI1369"
manufacturer = "AMD"
datasheet = "https://docs.amd.com/r/en-US/am013-versal-pkg-pinout"
reference_designator_prefix = "U"
# --- Bank 103 ---
GTY_REFCLKN0_103 = Port()
GTY_REFCLKN1_103 = Port()
GTY_REFCLKP0_103 = Port()
GTY_REFCLKP1_103 = Port()
GTY_RXN0_103 = Port()
GTY_RXN1_103 = Port()
GTY_RXN2_103 = Port()
GTY_RXN3_103 = Port()
GTY_RXP0_103 = Port()
GTY_RXP1_103 = Port()
GTY_RXP2_103 = Port()
GTY_RXP3_103 = Port()
GTY_TXN0_103 = Port()
GTY_TXN1_103 = Port()
GTY_TXN2_103 = Port()
GTY_TXN3_103 = Port()
GTY_TXP0_103 = Port()
GTY_TXP1_103 = Port()
GTY_TXP2_103 = Port()
GTY_TXP3_103 = Port()
# --- Bank 105 ---
GTY_AVTTRCAL_RS = Port()
GTY_REFCLKN0_105 = Port()
GTY_REFCLKN1_105 = Port()
GTY_REFCLKP0_105 = Port()
GTY_REFCLKP1_105 = Port()
GTY_RREF_RS = Port()
GTY_RXN0_105 = Port()
GTY_RXN1_105 = Port()
GTY_RXN2_105 = Port()
GTY_RXN3_105 = Port()
GTY_RXP0_105 = Port()
GTY_RXP1_105 = Port()
GTY_RXP2_105 = Port()
GTY_RXP3_105 = Port()
GTY_TXN0_105 = Port()
GTY_TXN1_105 = Port()
GTY_TXN2_105 = Port()
GTY_TXN3_105 = Port()
GTY_TXP0_105 = Port()
GTY_TXP1_105 = Port()
GTY_TXP2_105 = Port()
GTY_TXP3_105 = Port()
# --- Bank 109 ---
GTM_AVTTRCAL_RN = Port()
GTM_RREF_RN = Port()
# --- Bank 202 ---
GTM_REFCLKN0_202 = Port()
GTM_REFCLKN1_202 = Port()
GTM_REFCLKP0_202 = Port()
GTM_REFCLKP1_202 = Port()
GTM_RXN0_202 = Port()
GTM_RXN1_202 = Port()
GTM_RXN2_202 = Port()
GTM_RXN3_202 = Port()
GTM_RXP0_202 = Port()
GTM_RXP1_202 = Port()
GTM_RXP2_202 = Port()
GTM_RXP3_202 = Port()
GTM_TXN0_202 = Port()
GTM_TXN1_202 = Port()
GTM_TXN2_202 = Port()
GTM_TXN3_202 = Port()
GTM_TXP0_202 = Port()
GTM_TXP1_202 = Port()
GTM_TXP2_202 = Port()
GTM_TXP3_202 = Port()
# --- Bank 203 ---
GTM_AVTTRCAL_L = Port()
GTM_REFCLKN0_203 = Port()
GTM_REFCLKN1_203 = Port()
GTM_REFCLKP0_203 = Port()
GTM_REFCLKP1_203 = Port()
GTM_RREF_L = Port()
GTM_RXN0_203 = Port()
GTM_RXN1_203 = Port()
GTM_RXN2_203 = Port()
GTM_RXN3_203 = Port()
GTM_RXP0_203 = Port()
GTM_RXP1_203 = Port()
GTM_RXP2_203 = Port()
GTM_RXP3_203 = Port()
GTM_TXN0_203 = Port()
GTM_TXN1_203 = Port()
GTM_TXN2_203 = Port()
GTM_TXN3_203 = Port()
GTM_TXP0_203 = Port()
GTM_TXP1_203 = Port()
GTM_TXP2_203 = Port()
GTM_TXP3_203 = Port()
# --- Bank 204 ---
GTM_REFCLKN0_204 = Port()
GTM_REFCLKN1_204 = Port()
GTM_REFCLKP0_204 = Port()
GTM_REFCLKP1_204 = Port()
GTM_RXN0_204 = Port()
GTM_RXN1_204 = Port()
GTM_RXN2_204 = Port()
GTM_RXN3_204 = Port()
GTM_RXP0_204 = Port()
GTM_RXP1_204 = Port()
GTM_RXP2_204 = Port()
GTM_RXP3_204 = Port()
GTM_TXN0_204 = Port()
GTM_TXN1_204 = Port()
GTM_TXN2_204 = Port()
GTM_TXN3_204 = Port()
GTM_TXP0_204 = Port()
GTM_TXP1_204 = Port()
GTM_TXP2_204 = Port()
GTM_TXP3_204 = Port()
# --- Bank 205 ---
GTM_REFCLKN0_205 = Port()
GTM_REFCLKN1_205 = Port()
GTM_REFCLKP0_205 = Port()
GTM_REFCLKP1_205 = Port()
GTM_RXN0_205 = Port()
GTM_RXN1_205 = Port()
GTM_RXN2_205 = Port()
GTM_RXN3_205 = Port()
GTM_RXP0_205 = Port()
GTM_RXP1_205 = Port()
GTM_RXP2_205 = Port()
GTM_RXP3_205 = Port()
GTM_TXN0_205 = Port()
GTM_TXN1_205 = Port()
GTM_TXN2_205 = Port()
GTM_TXN3_205 = Port()
GTM_TXP0_205 = Port()
GTM_TXP1_205 = Port()
GTM_TXP2_205 = Port()
GTM_TXP3_205 = Port()
# --- Bank 206 ---
GTM_REFCLKN0_206 = Port()
GTM_REFCLKN1_206 = Port()
GTM_REFCLKP0_206 = Port()
GTM_REFCLKP1_206 = Port()
GTM_RXN0_206 = Port()
GTM_RXN1_206 = Port()
GTM_RXN2_206 = Port()
GTM_RXN3_206 = Port()
GTM_RXP0_206 = Port()
GTM_RXP1_206 = Port()
GTM_RXP2_206 = Port()
GTM_RXP3_206 = Port()
GTM_TXN0_206 = Port()
GTM_TXN1_206 = Port()
GTM_TXN2_206 = Port()
GTM_TXN3_206 = Port()
GTM_TXP0_206 = Port()
GTM_TXP1_206 = Port()
GTM_TXP2_206 = Port()
GTM_TXP3_206 = Port()
# --- Bank 207 ---
GTM_REFCLKN0_207 = Port()
GTM_REFCLKN1_207 = Port()
GTM_REFCLKP0_207 = Port()
GTM_REFCLKP1_207 = Port()
GTM_RXN0_207 = Port()
GTM_RXN1_207 = Port()
GTM_RXN2_207 = Port()
GTM_RXN3_207 = Port()
GTM_RXP0_207 = Port()
GTM_RXP1_207 = Port()
GTM_RXP2_207 = Port()
GTM_RXP3_207 = Port()
GTM_TXN0_207 = Port()
GTM_TXN1_207 = Port()
GTM_TXN2_207 = Port()
GTM_TXN3_207 = Port()
GTM_TXP0_207 = Port()
GTM_TXP1_207 = Port()
GTM_TXP2_207 = Port()
GTM_TXP3_207 = Port()
# --- Bank 500 ---
PMC_MIO0_500 = Port()
PMC_MIO1_500 = Port()
PMC_MIO2_500 = Port()
PMC_MIO3_500 = Port()
PMC_MIO4_500 = Port()
PMC_MIO5_500 = Port()
PMC_MIO6_500 = Port()
PMC_MIO7_500 = Port()
PMC_MIO8_500 = Port()
PMC_MIO9_500 = Port()
PMC_MIO10_500 = Port()
PMC_MIO11_500 = Port()
PMC_MIO12_500 = Port()
PMC_MIO13_500 = Port()
PMC_MIO14_500 = Port()
PMC_MIO15_500 = Port()
PMC_MIO16_500 = Port()
PMC_MIO17_500 = Port()
PMC_MIO18_500 = Port()
PMC_MIO19_500 = Port()
PMC_MIO20_500 = Port()
PMC_MIO21_500 = Port()
PMC_MIO22_500 = Port()
PMC_MIO23_500 = Port()
PMC_MIO24_500 = Port()
PMC_MIO25_500 = Port()
# --- Bank 501 ---
PMC_MIO26_501 = Port()
PMC_MIO27_501 = Port()
PMC_MIO28_501 = Port()
PMC_MIO29_501 = Port()
PMC_MIO30_501 = Port()
PMC_MIO31_501 = Port()
PMC_MIO32_501 = Port()
PMC_MIO33_501 = Port()
PMC_MIO34_501 = Port()
PMC_MIO35_501 = Port()
PMC_MIO36_501 = Port()
PMC_MIO37_501 = Port()
PMC_MIO38_501 = Port()
PMC_MIO39_501 = Port()
PMC_MIO40_501 = Port()
PMC_MIO41_501 = Port()
PMC_MIO42_501 = Port()
PMC_MIO43_501 = Port()
PMC_MIO44_501 = Port()
PMC_MIO45_501 = Port()
PMC_MIO46_501 = Port()
PMC_MIO47_501 = Port()
PMC_MIO48_501 = Port()
PMC_MIO49_501 = Port()
PMC_MIO50_501 = Port()
PMC_MIO51_501 = Port()
# --- Bank 502 ---
LPD_MIO0_502 = Port()
LPD_MIO1_502 = Port()
LPD_MIO2_502 = Port()
LPD_MIO3_502 = Port()
LPD_MIO4_502 = Port()
LPD_MIO5_502 = Port()
LPD_MIO6_502 = Port()
LPD_MIO7_502 = Port()
LPD_MIO8_502 = Port()
LPD_MIO9_502 = Port()
LPD_MIO10_502 = Port()
LPD_MIO11_502 = Port()
LPD_MIO12_502 = Port()
LPD_MIO13_502 = Port()
LPD_MIO14_502 = Port()
LPD_MIO15_502 = Port()
LPD_MIO16_502 = Port()
LPD_MIO17_502 = Port()
LPD_MIO18_502 = Port()
LPD_MIO19_502 = Port()
LPD_MIO20_502 = Port()
LPD_MIO21_502 = Port()
LPD_MIO22_502 = Port()
LPD_MIO23_502 = Port()
LPD_MIO24_502 = Port()
LPD_MIO25_502 = Port()
# --- Bank 503 ---
DONE_503 = Port()
ERROR_OUT_503 = Port()
MODE0_503 = Port()
MODE1_503 = Port()
MODE2_503 = Port()
MODE3_503 = Port()
POR_B_503 = Port()
PUDC_B_503 = Port()
REF_CLK_503 = Port()
RTC_PADI_503 = Port()
RTC_PADO_503 = Port()
TCK_503 = Port()
TDI_503 = Port()
TDO_503 = Port()
TMS_503 = Port()
# --- Bank 700 ---
IO_L0N_XCC_N0P1_M0P1_700 = Port()
IO_L0P_XCC_N0P0_M0P0_700 = Port()
IO_L1N_N0P3_M0P3_700 = Port()
IO_L1P_N0P2_M0P2_700 = Port()
IO_L2N_N0P5_M0P5_700 = Port()
IO_L2P_N0P4_M0P4_700 = Port()
IO_L3N_XCC_N1P1_M0P7_700 = Port()
IO_L3P_XCC_N1P0_M0P6_700 = Port()
IO_L4N_N1P3_M0P9_700 = Port()
IO_L4P_N1P2_M0P8_700 = Port()
IO_L5N_N1P5_M0P11_700 = Port()
IO_L5P_N1P4_M0P10_700 = Port()
IO_L6N_GC_XCC_N2P1_M0P13_700 = Port()
IO_L6P_GC_XCC_N2P0_M0P12_700 = Port()
IO_L7N_N2P3_M0P15_700 = Port()
IO_L7P_N2P2_M0P14_700 = Port()
IO_L8N_N2P5_M0P17_700 = Port()
IO_L8P_N2P4_M0P16_700 = Port()
IO_L9N_GC_XCC_N3P1_M0P19_700 = Port()
IO_L9P_GC_XCC_N3P0_M0P18_700 = Port()
IO_L10N_N3P3_M0P21_700 = Port()
IO_L10P_N3P2_M0P20_700 = Port()
IO_L11N_N3P5_M0P23_700 = Port()
IO_L11P_N3P4_M0P22_700 = Port()
IO_L12N_GC_XCC_N4P1_M0P25_700 = Port()
IO_L12P_GC_XCC_N4P0_M0P24_700 = Port()
IO_L13N_N4P3_M0P27_700 = Port()
IO_L13P_N4P2_M0P26_700 = Port()
IO_L14N_N4P5_M0P29_700 = Port()
IO_L14P_N4P4_M0P28_700 = Port()
IO_L15N_XCC_N5P1_M0P31_700 = Port()
IO_L15P_XCC_N5P0_M0P30_700 = Port()
IO_L16N_N5P3_M0P33_700 = Port()
IO_L16P_N5P2_M0P32_700 = Port()
IO_L17N_N5P5_M0P35_700 = Port()
IO_L17P_N5P4_M0P34_700 = Port()
IO_L18N_XCC_N6P1_M0P37_700 = Port()
IO_L18P_XCC_N6P0_M0P36_700 = Port()
IO_L19N_N6P3_M0P39_700 = Port()
IO_L19P_N6P2_M0P38_700 = Port()
IO_L20N_N6P5_M0P41_700 = Port()
IO_L20P_N6P4_M0P40_700 = Port()
IO_L21N_XCC_N7P1_M0P43_700 = Port()
IO_L21P_XCC_N7P0_M0P42_700 = Port()
IO_L22N_N7P3_M0P45_700 = Port()
IO_L22P_N7P2_M0P44_700 = Port()
IO_L23N_N7P5_M0P47_700 = Port()
IO_L23P_N7P4_M0P46_700 = Port()
IO_L24N_GC_XCC_N8P1_M0P49_700 = Port()
IO_L24P_GC_XCC_N8P0_M0P48_700 = Port()
IO_L25N_N8P3_M0P51_700 = Port()
IO_L25P_N8P2_M0P50_700 = Port()
IO_L26N_N8P5_M0P53_700 = Port()
IO_L26P_N8P4_M0P52_700 = Port()
IO_VR_700 = Port()
# --- Bank 701 ---
IO_L0N_XCC_N0P1_M0P55_701 = Port()
IO_L0P_XCC_N0P0_M0P54_701 = Port()
IO_L1N_N0P3_M0P57_701 = Port()
IO_L1P_N0P2_M0P56_701 = Port()
IO_L2N_N0P5_M0P59_701 = Port()
IO_L2P_N0P4_M0P58_701 = Port()
IO_L3N_XCC_N1P1_M0P61_701 = Port()
IO_L3P_XCC_N1P0_M0P60_701 = Port()
IO_L4N_N1P3_M0P63_701 = Port()
IO_L4P_N1P2_M0P62_701 = Port()
IO_L5N_N1P5_M0P65_701 = Port()
IO_L5P_N1P4_M0P64_701 = Port()
IO_L6N_GC_XCC_N2P1_M0P67_701 = Port()
IO_L6P_GC_XCC_N2P0_M0P66_701 = Port()
IO_L7N_N2P3_M0P69_701 = Port()
IO_L7P_N2P2_M0P68_701 = Port()
IO_L8N_N2P5_M0P71_701 = Port()
IO_L8P_N2P4_M0P70_701 = Port()
IO_L9N_GC_XCC_N3P1_M0P73_701 = Port()
IO_L9P_GC_XCC_N3P0_M0P72_701 = Port()
IO_L10N_N3P3_M0P75_701 = Port()
IO_L10P_N3P2_M0P74_701 = Port()
IO_L11N_N3P5_M0P77_701 = Port()
IO_L11P_N3P4_M0P76_701 = Port()
IO_L12N_GC_XCC_N4P1_M0P79_701 = Port()
IO_L12P_GC_XCC_N4P0_M0P78_701 = Port()
IO_L13N_N4P3_M0P81_701 = Port()
IO_L13P_N4P2_M0P80_701 = Port()
IO_L14N_N4P5_M0P83_701 = Port()
IO_L14P_N4P4_M0P82_701 = Port()
IO_L15N_XCC_N5P1_M0P85_701 = Port()
IO_L15P_XCC_N5P0_M0P84_701 = Port()
IO_L16N_N5P3_M0P87_701 = Port()
IO_L16P_N5P2_M0P86_701 = Port()
IO_L17N_N5P5_M0P89_701 = Port()
IO_L17P_N5P4_M0P88_701 = Port()
IO_L18N_XCC_N6P1_M0P91_701 = Port()
IO_L18P_XCC_N6P0_M0P90_701 = Port()
IO_L19N_N6P3_M0P93_701 = Port()
IO_L19P_N6P2_M0P92_701 = Port()
IO_L20N_N6P5_M0P95_701 = Port()
IO_L20P_N6P4_M0P94_701 = Port()
IO_L21N_XCC_N7P1_M0P97_701 = Port()
IO_L21P_XCC_N7P0_M0P96_701 = Port()
IO_L22N_N7P3_M0P99_701 = Port()
IO_L22P_N7P2_M0P98_701 = Port()
IO_L23N_N7P5_M0P101_701 = Port()
IO_L23P_N7P4_M0P100_701 = Port()
IO_L24N_GC_XCC_N8P1_M0P103_701 = Port()
IO_L24P_GC_XCC_N8P0_M0P102_701 = Port()
IO_L25N_N8P3_M0P105_701 = Port()
IO_L25P_N8P2_M0P104_701 = Port()
IO_L26N_N8P5_M0P107_701 = Port()
IO_L26P_N8P4_M0P106_701 = Port()
# --- Bank 702 ---
IO_L0N_XCC_N0P1_M0P109_702 = Port()
IO_L0P_XCC_N0P0_M0P108_702 = Port()
IO_L1N_N0P3_M0P111_702 = Port()
IO_L1P_N0P2_M0P110_702 = Port()
IO_L2N_N0P5_M0P113_702 = Port()
IO_L2P_N0P4_M0P112_702 = Port()
IO_L3N_XCC_N1P1_M0P115_702 = Port()
IO_L3P_XCC_N1P0_M0P114_702 = Port()
IO_L4N_N1P3_M0P117_702 = Port()
IO_L4P_N1P2_M0P116_702 = Port()
IO_L5N_N1P5_M0P119_702 = Port()
IO_L5P_N1P4_M0P118_702 = Port()
IO_L6N_GC_XCC_N2P1_M0P121_702 = Port()
IO_L6P_GC_XCC_N2P0_M0P120_702 = Port()
IO_L7N_N2P3_M0P123_702 = Port()
IO_L7P_N2P2_M0P122_702 = Port()
IO_L8N_N2P5_M0P125_702 = Port()
IO_L8P_N2P4_M0P124_702 = Port()
IO_L9N_GC_XCC_N3P1_M0P127_702 = Port()
IO_L9P_GC_XCC_N3P0_M0P126_702 = Port()
IO_L10N_N3P3_M0P129_702 = Port()
IO_L10P_N3P2_M0P128_702 = Port()
IO_L11N_N3P5_M0P131_702 = Port()
IO_L11P_N3P4_M0P130_702 = Port()
IO_L12N_GC_XCC_N4P1_M0P133_702 = Port()
IO_L12P_GC_XCC_N4P0_M0P132_702 = Port()
IO_L13N_N4P3_M0P135_702 = Port()
IO_L13P_N4P2_M0P134_702 = Port()
IO_L14N_N4P5_M0P137_702 = Port()
IO_L14P_N4P4_M0P136_702 = Port()
IO_L15N_XCC_N5P1_M0P139_702 = Port()
IO_L15P_XCC_N5P0_M0P138_702 = Port()
IO_L16N_N5P3_M0P141_702 = Port()
IO_L16P_N5P2_M0P140_702 = Port()
IO_L17N_N5P5_M0P143_702 = Port()
IO_L17P_N5P4_M0P142_702 = Port()
IO_L18N_XCC_N6P1_M0P145_702 = Port()
IO_L18P_XCC_N6P0_M0P144_702 = Port()
IO_L19N_N6P3_M0P147_702 = Port()
IO_L19P_N6P2_M0P146_702 = Port()
IO_L20N_N6P5_M0P149_702 = Port()
IO_L20P_N6P4_M0P148_702 = Port()
IO_L21N_XCC_N7P1_M0P151_702 = Port()
IO_L21P_XCC_N7P0_M0P150_702 = Port()
IO_L22N_N7P3_M0P153_702 = Port()
IO_L22P_N7P2_M0P152_702 = Port()
IO_L23N_N7P5_M0P155_702 = Port()
IO_L23P_N7P4_M0P154_702 = Port()
IO_L24N_GC_XCC_N8P1_M0P157_702 = Port()
IO_L24P_GC_XCC_N8P0_M0P156_702 = Port()
IO_L25N_N8P3_M0P159_702 = Port()
IO_L25P_N8P2_M0P158_702 = Port()
IO_L26N_N8P5_M0P161_702 = Port()
IO_L26P_N8P4_M0P160_702 = Port()
# --- Dedicated / bankless ---
GND_SENSE = Port()
GND_SMON = Port()
VCCAUX_SMON = Port()
VCCINT_SENSE = Port()
VCC_BATT = Port()
VCC_FUSE = Port()
VN_500 = Port()
VP_500 = Port()
VREFN_500 = Port()
VREFP_500 = Port()
# --- Repeated rails (indexed lists, (row, col) order) ---
GND = [Port() for _ in range(689)]
GTM_AVCCAUX_L = [Port() for _ in range(2)]
GTM_AVCCAUX_RN = [Port() for _ in range(2)]
GTM_AVCC_L = [Port() for _ in range(6)]
GTM_AVCC_RN = [Port() for _ in range(3)]
GTM_AVTT_L = [Port() for _ in range(8)]
GTM_AVTT_RN = [Port() for _ in range(4)]
GTY_AVCCAUX_RS = [Port() for _ in range(2)]
GTY_AVCC_RS = [Port() for _ in range(2)]
GTY_AVTT_RS = [Port() for _ in range(4)]
NC = [Port() for _ in range(60)]
RSVDGND = [Port() for _ in range(2)]
VCCAUX = [Port() for _ in range(6)]
VCCAUX_PMC = [Port() for _ in range(2)]
VCCINT = [Port() for _ in range(84)]
VCCINT_GT_L = [Port() for _ in range(5)]
VCCINT_GT_R = [Port() for _ in range(3)]
VCCO_500 = [Port() for _ in range(2)]
VCCO_501 = [Port() for _ in range(2)]
VCCO_502 = [Port() for _ in range(2)]
VCCO_503 = [Port() for _ in range(2)]
VCCO_700 = [Port() for _ in range(3)]
VCCO_701 = [Port() for _ in range(3)]
VCCO_702 = [Port() for _ in range(3)]
VCC_IO = [Port() for _ in range(2)]
VCC_PMC = [Port() for _ in range(3)]
VCC_PSFP = [Port() for _ in range(4)]
VCC_PSLP = [Port() for _ in range(3)]
VCC_RAM = [Port() for _ in range(6)]
VCC_SOC = [Port() for _ in range(18)]
landpattern = make_landpattern(NFVI1369)
[docs]
def ball_assignments(self) -> Iterator[tuple[Port, tuple[int, int]]]:
"""Yield every (port, zero-indexed grid coordinate) pair."""
# Bank 103
yield self.GTY_REFCLKN0_103, (25, 5) # AF6
yield self.GTY_REFCLKN1_103, (23, 5) # AD6
yield self.GTY_REFCLKP0_103, (25, 6) # AF7
yield self.GTY_REFCLKP1_103, (23, 6) # AD7
yield self.GTY_RXN0_103, (31, 2) # AM3
yield self.GTY_RXN1_103, (30, 0) # AL1
yield self.GTY_RXN2_103, (29, 2) # AK3
yield self.GTY_RXN3_103, (28, 0) # AJ1
yield self.GTY_RXP0_103, (31, 3) # AM4
yield self.GTY_RXP1_103, (30, 1) # AL2
yield self.GTY_RXP2_103, (29, 3) # AK4
yield self.GTY_RXP3_103, (28, 1) # AJ2
yield self.GTY_TXN0_103, (36, 2) # AU3
yield self.GTY_TXN1_103, (35, 0) # AT1
yield self.GTY_TXN2_103, (34, 2) # AR3
yield self.GTY_TXN3_103, (33, 0) # AP1
yield self.GTY_TXP0_103, (36, 3) # AU4
yield self.GTY_TXP1_103, (35, 1) # AT2
yield self.GTY_TXP2_103, (34, 3) # AR4
yield self.GTY_TXP3_103, (33, 1) # AP2
# Bank 105
yield self.GTY_AVTTRCAL_RS, (21, 5) # AB6
yield self.GTY_REFCLKN0_105, (20, 7) # AA8
yield self.GTY_REFCLKN1_105, (19, 5) # Y6
yield self.GTY_REFCLKP0_105, (20, 8) # AA9
yield self.GTY_REFCLKP1_105, (19, 6) # Y7
yield self.GTY_RREF_RS, (21, 6) # AB7
yield self.GTY_RXN0_105, (27, 2) # AH3
yield self.GTY_RXN1_105, (26, 0) # AG1
yield self.GTY_RXN2_105, (25, 2) # AF3
yield self.GTY_RXN3_105, (24, 0) # AE1
yield self.GTY_RXP0_105, (27, 3) # AH4
yield self.GTY_RXP1_105, (26, 1) # AG2
yield self.GTY_RXP2_105, (25, 3) # AF4
yield self.GTY_RXP3_105, (24, 1) # AE2
yield self.GTY_TXN0_105, (22, 2) # AC3
yield self.GTY_TXN1_105, (21, 0) # AB1
yield self.GTY_TXN2_105, (20, 2) # AA3
yield self.GTY_TXN3_105, (19, 0) # Y1
yield self.GTY_TXP0_105, (22, 3) # AC4
yield self.GTY_TXP1_105, (21, 1) # AB2
yield self.GTY_TXP2_105, (20, 3) # AA4
yield self.GTY_TXP3_105, (19, 1) # Y2
# Bank 109
yield self.GTM_AVTTRCAL_RN, (15, 9) # T10
yield self.GTM_RREF_RN, (15, 10) # T11
# Bank 202
yield self.GTM_REFCLKN0_202, (22, 27) # AC28
yield self.GTM_REFCLKN1_202, (20, 27) # AA28
yield self.GTM_REFCLKP0_202, (22, 26) # AC27
yield self.GTM_REFCLKP1_202, (20, 26) # AA27
yield self.GTM_RXN0_202, (32, 35) # AN36
yield self.GTM_RXN1_202, (30, 35) # AL36
yield self.GTM_RXN2_202, (28, 35) # AJ36
yield self.GTM_RXN3_202, (27, 33) # AH34
yield self.GTM_RXP0_202, (32, 34) # AN35
yield self.GTM_RXP1_202, (30, 34) # AL35
yield self.GTM_RXP2_202, (28, 34) # AJ35
yield self.GTM_RXP3_202, (27, 32) # AH33
yield self.GTM_TXN0_202, (31, 32) # AM33
yield self.GTM_TXN1_202, (30, 30) # AL31
yield self.GTM_TXN2_202, (29, 32) # AK33
yield self.GTM_TXN3_202, (28, 30) # AJ31
yield self.GTM_TXP0_202, (31, 31) # AM32
yield self.GTM_TXP1_202, (30, 29) # AL30
yield self.GTM_TXP2_202, (29, 31) # AK32
yield self.GTM_TXP3_202, (28, 29) # AJ30
# Bank 203
yield self.GTM_AVTTRCAL_L, (18, 27) # W28
yield self.GTM_REFCLKN0_203, (16, 27) # U28
yield self.GTM_REFCLKN1_203, (14, 27) # R28
yield self.GTM_REFCLKP0_203, (16, 26) # U27
yield self.GTM_REFCLKP1_203, (14, 26) # R27
yield self.GTM_RREF_L, (18, 26) # W27
yield self.GTM_RXN0_203, (26, 35) # AG36
yield self.GTM_RXN1_203, (25, 33) # AF34
yield self.GTM_RXN2_203, (24, 35) # AE36
yield self.GTM_RXN3_203, (23, 33) # AD34
yield self.GTM_RXP0_203, (26, 34) # AG35
yield self.GTM_RXP1_203, (25, 32) # AF33
yield self.GTM_RXP2_203, (24, 34) # AE35
yield self.GTM_RXP3_203, (23, 32) # AD33
yield self.GTM_TXN0_203, (26, 30) # AG31
yield self.GTM_TXN1_203, (24, 30) # AE31
yield self.GTM_TXN2_203, (22, 30) # AC31
yield self.GTM_TXN3_203, (21, 32) # AB33
yield self.GTM_TXP0_203, (26, 29) # AG30
yield self.GTM_TXP1_203, (24, 29) # AE30
yield self.GTM_TXP2_203, (22, 29) # AC30
yield self.GTM_TXP3_203, (21, 31) # AB32
# Bank 204
yield self.GTM_REFCLKN0_204, (12, 27) # N28
yield self.GTM_REFCLKN1_204, (11, 25) # M26
yield self.GTM_REFCLKP0_204, (12, 26) # N27
yield self.GTM_REFCLKP1_204, (11, 24) # M25
yield self.GTM_RXN0_204, (22, 35) # AC36
yield self.GTM_RXN1_204, (20, 35) # AA36
yield self.GTM_RXN2_204, (18, 35) # W36
yield self.GTM_RXN3_204, (16, 35) # U36
yield self.GTM_RXP0_204, (22, 34) # AC35
yield self.GTM_RXP1_204, (20, 34) # AA35
yield self.GTM_RXP2_204, (18, 34) # W35
yield self.GTM_RXP3_204, (16, 34) # U35
yield self.GTM_TXN0_204, (20, 30) # AA31
yield self.GTM_TXN1_204, (19, 32) # Y33
yield self.GTM_TXN2_204, (18, 30) # W31
yield self.GTM_TXN3_204, (17, 32) # V33
yield self.GTM_TXP0_204, (20, 29) # AA30
yield self.GTM_TXP1_204, (19, 31) # Y32
yield self.GTM_TXP2_204, (18, 29) # W30
yield self.GTM_TXP3_204, (17, 31) # V32
# Bank 205
yield self.GTM_REFCLKN0_205, (10, 27) # L28
yield self.GTM_REFCLKN1_205, (9, 25) # K26
yield self.GTM_REFCLKP0_205, (10, 26) # L27
yield self.GTM_REFCLKP1_205, (9, 24) # K25
yield self.GTM_RXN0_205, (14, 35) # R36
yield self.GTM_RXN1_205, (12, 35) # N36
yield self.GTM_RXN2_205, (10, 35) # L36
yield self.GTM_RXN3_205, (9, 33) # K34
yield self.GTM_RXP0_205, (14, 34) # R35
yield self.GTM_RXP1_205, (12, 34) # N35
yield self.GTM_RXP2_205, (10, 34) # L35
yield self.GTM_RXP3_205, (9, 32) # K33
yield self.GTM_TXN0_205, (16, 30) # U31
yield self.GTM_TXN1_205, (15, 32) # T33
yield self.GTM_TXN2_205, (14, 30) # R31
yield self.GTM_TXN3_205, (13, 32) # P33
yield self.GTM_TXP0_205, (16, 29) # U30
yield self.GTM_TXP1_205, (15, 31) # T32
yield self.GTM_TXP2_205, (14, 29) # R30
yield self.GTM_TXP3_205, (13, 31) # P32
# Bank 206
yield self.GTM_REFCLKN0_206, (8, 27) # J28
yield self.GTM_REFCLKN1_206, (7, 25) # H26
yield self.GTM_REFCLKP0_206, (8, 26) # J27
yield self.GTM_REFCLKP1_206, (7, 24) # H25
yield self.GTM_RXN0_206, (8, 35) # J36
yield self.GTM_RXN1_206, (7, 33) # H34
yield self.GTM_RXN2_206, (6, 35) # G36
yield self.GTM_RXN3_206, (5, 33) # F34
yield self.GTM_RXP0_206, (8, 34) # J35
yield self.GTM_RXP1_206, (7, 32) # H33
yield self.GTM_RXP2_206, (6, 34) # G35
yield self.GTM_RXP3_206, (5, 32) # F33
yield self.GTM_TXN0_206, (12, 30) # N31
yield self.GTM_TXN1_206, (11, 32) # M33
yield self.GTM_TXN2_206, (10, 30) # L31
yield self.GTM_TXN3_206, (8, 30) # J31
yield self.GTM_TXP0_206, (12, 29) # N30
yield self.GTM_TXP1_206, (11, 31) # M32
yield self.GTM_TXP2_206, (10, 29) # L30
yield self.GTM_TXP3_206, (8, 29) # J30
# Bank 207
yield self.GTM_REFCLKN0_207, (6, 27) # G28
yield self.GTM_REFCLKN1_207, (4, 27) # E28
yield self.GTM_REFCLKP0_207, (6, 26) # G27
yield self.GTM_REFCLKP1_207, (4, 26) # E27
yield self.GTM_RXN0_207, (4, 35) # E36
yield self.GTM_RXN1_207, (3, 33) # D34
yield self.GTM_RXN2_207, (2, 35) # C36
yield self.GTM_RXN3_207, (1, 33) # B34
yield self.GTM_RXP0_207, (4, 34) # E35
yield self.GTM_RXP1_207, (3, 32) # D33
yield self.GTM_RXP2_207, (2, 34) # C35
yield self.GTM_RXP3_207, (1, 32) # B33
yield self.GTM_TXN0_207, (6, 30) # G31
yield self.GTM_TXN1_207, (4, 30) # E31
yield self.GTM_TXN2_207, (2, 30) # C31
yield self.GTM_TXN3_207, (1, 28) # B29
yield self.GTM_TXP0_207, (6, 29) # G30
yield self.GTM_TXP1_207, (4, 29) # E30
yield self.GTM_TXP2_207, (2, 29) # C30
yield self.GTM_TXP3_207, (1, 27) # B28
# Bank 500
yield self.PMC_MIO0_500, (5, 16) # F17
yield self.PMC_MIO1_500, (6, 16) # G17
yield self.PMC_MIO2_500, (5, 15) # F16
yield self.PMC_MIO3_500, (4, 15) # E16
yield self.PMC_MIO4_500, (3, 15) # D16
yield self.PMC_MIO5_500, (4, 14) # E15
yield self.PMC_MIO6_500, (5, 14) # F15
yield self.PMC_MIO7_500, (6, 14) # G15
yield self.PMC_MIO8_500, (6, 13) # G14
yield self.PMC_MIO9_500, (4, 13) # E14
yield self.PMC_MIO10_500, (3, 13) # D14
yield self.PMC_MIO11_500, (3, 12) # D13
yield self.PMC_MIO12_500, (4, 12) # E13
yield self.PMC_MIO13_500, (5, 12) # F13
yield self.PMC_MIO14_500, (6, 12) # G13
yield self.PMC_MIO15_500, (6, 11) # G12
yield self.PMC_MIO16_500, (5, 11) # F12
yield self.PMC_MIO17_500, (3, 11) # D12
yield self.PMC_MIO18_500, (2, 11) # C12
yield self.PMC_MIO19_500, (2, 10) # C11
yield self.PMC_MIO20_500, (3, 10) # D11
yield self.PMC_MIO21_500, (4, 10) # E11
yield self.PMC_MIO22_500, (5, 10) # F11
yield self.PMC_MIO23_500, (5, 9) # F10
yield self.PMC_MIO24_500, (4, 9) # E10
yield self.PMC_MIO25_500, (3, 9) # D10
# Bank 501
yield self.PMC_MIO26_501, (3, 24) # D25
yield self.PMC_MIO27_501, (4, 24) # E25
yield self.PMC_MIO28_501, (5, 24) # F25
yield self.PMC_MIO29_501, (4, 23) # E24
yield self.PMC_MIO30_501, (3, 23) # D24
yield self.PMC_MIO31_501, (3, 22) # D23
yield self.PMC_MIO32_501, (4, 22) # E23
yield self.PMC_MIO33_501, (5, 22) # F23
yield self.PMC_MIO34_501, (6, 22) # G23
yield self.PMC_MIO35_501, (6, 21) # G22
yield self.PMC_MIO36_501, (5, 21) # F22
yield self.PMC_MIO37_501, (3, 21) # D22
yield self.PMC_MIO38_501, (3, 20) # D21
yield self.PMC_MIO39_501, (4, 20) # E21
yield self.PMC_MIO40_501, (5, 20) # F21
yield self.PMC_MIO41_501, (6, 19) # G20
yield self.PMC_MIO42_501, (5, 19) # F20
yield self.PMC_MIO43_501, (4, 19) # E20
yield self.PMC_MIO44_501, (3, 18) # D19
yield self.PMC_MIO45_501, (4, 18) # E19
yield self.PMC_MIO46_501, (6, 18) # G19
yield self.PMC_MIO47_501, (6, 17) # G18
yield self.PMC_MIO48_501, (5, 17) # F18
yield self.PMC_MIO49_501, (4, 17) # E18
yield self.PMC_MIO50_501, (3, 17) # D18
yield self.PMC_MIO51_501, (3, 16) # D17
# Bank 502
yield self.LPD_MIO0_502, (2, 20) # C21
yield self.LPD_MIO1_502, (2, 19) # C20
yield self.LPD_MIO2_502, (1, 19) # B20
yield self.LPD_MIO3_502, (0, 19) # A20
yield self.LPD_MIO4_502, (2, 18) # C19
yield self.LPD_MIO5_502, (1, 18) # B19
yield self.LPD_MIO6_502, (0, 17) # A18
yield self.LPD_MIO7_502, (1, 17) # B18
yield self.LPD_MIO8_502, (2, 16) # C17
yield self.LPD_MIO9_502, (1, 16) # B17
yield self.LPD_MIO10_502, (0, 16) # A17
yield self.LPD_MIO11_502, (0, 15) # A16
yield self.LPD_MIO12_502, (2, 15) # C16
yield self.LPD_MIO13_502, (0, 14) # A15
yield self.LPD_MIO14_502, (1, 14) # B15
yield self.LPD_MIO15_502, (2, 14) # C15
yield self.LPD_MIO16_502, (2, 13) # C14
yield self.LPD_MIO17_502, (1, 13) # B14
yield self.LPD_MIO18_502, (0, 12) # A13
yield self.LPD_MIO19_502, (1, 12) # B13
yield self.LPD_MIO20_502, (0, 11) # A12
yield self.LPD_MIO21_502, (1, 11) # B12
yield self.LPD_MIO22_502, (0, 10) # A11
yield self.LPD_MIO23_502, (0, 9) # A10
yield self.LPD_MIO24_502, (1, 9) # B10
yield self.LPD_MIO25_502, (2, 9) # C10
# Bank 503
yield self.DONE_503, (2, 21) # C22
yield self.ERROR_OUT_503, (0, 20) # A21
yield self.MODE0_503, (1, 24) # B25
yield self.MODE1_503, (1, 23) # B24
yield self.MODE2_503, (1, 22) # B23
yield self.MODE3_503, (1, 21) # B22
yield self.POR_B_503, (23, 15) # AD16
yield self.PUDC_B_503, (2, 23) # C24
yield self.REF_CLK_503, (22, 15) # AC16
yield self.RTC_PADI_503, (0, 24) # A25
yield self.RTC_PADO_503, (0, 25) # A26
yield self.TCK_503, (2, 24) # C25
yield self.TDI_503, (0, 21) # A22
yield self.TDO_503, (0, 22) # A23
yield self.TMS_503, (2, 25) # C26
# Bank 700
yield self.IO_L0N_XCC_N0P1_M0P1_700, (35, 10) # AT11
yield self.IO_L0P_XCC_N0P0_M0P0_700, (35, 9) # AT10
yield self.IO_L1N_N0P3_M0P3_700, (35, 12) # AT13
yield self.IO_L1P_N0P2_M0P2_700, (35, 11) # AT12
yield self.IO_L2N_N0P5_M0P5_700, (36, 14) # AU15
yield self.IO_L2P_N0P4_M0P4_700, (36, 13) # AU14
yield self.IO_L3N_XCC_N1P1_M0P7_700, (36, 12) # AU13
yield self.IO_L3P_XCC_N1P0_M0P6_700, (36, 11) # AU12
yield self.IO_L4N_N1P3_M0P9_700, (36, 9) # AU10
yield self.IO_L4P_N1P2_M0P8_700, (36, 8) # AU9
yield self.IO_L5N_N1P5_M0P11_700, (36, 7) # AU8
yield self.IO_L5P_N1P4_M0P10_700, (36, 6) # AU7
yield self.IO_L6N_GC_XCC_N2P1_M0P13_700, (34, 10) # AR11
yield self.IO_L6P_GC_XCC_N2P0_M0P12_700, (33, 10) # AP11
yield self.IO_L7N_N2P3_M0P15_700, (33, 13) # AP14
yield self.IO_L7P_N2P2_M0P14_700, (33, 12) # AP13
yield self.IO_L8N_N2P5_M0P17_700, (34, 13) # AR14
yield self.IO_L8P_N2P4_M0P16_700, (34, 12) # AR13
yield self.IO_L9N_GC_XCC_N3P1_M0P19_700, (34, 9) # AR10
yield self.IO_L9P_GC_XCC_N3P0_M0P18_700, (34, 8) # AR9
yield self.IO_L10N_N3P3_M0P21_700, (35, 5) # AT6
yield self.IO_L10P_N3P2_M0P20_700, (34, 5) # AR6
yield self.IO_L11N_N3P5_M0P23_700, (35, 7) # AT8
yield self.IO_L11P_N3P4_M0P22_700, (35, 6) # AT7
yield self.IO_L12N_GC_XCC_N4P1_M0P25_700, (30, 13) # AL14
yield self.IO_L12P_GC_XCC_N4P0_M0P24_700, (29, 12) # AK13
yield self.IO_L13N_N4P3_M0P27_700, (31, 10) # AM11
yield self.IO_L13P_N4P2_M0P26_700, (30, 10) # AL11
yield self.IO_L14N_N4P5_M0P29_700, (31, 7) # AM8
yield self.IO_L14P_N4P4_M0P28_700, (30, 7) # AL8
yield self.IO_L15N_XCC_N5P1_M0P31_700, (31, 6) # AM7
yield self.IO_L15P_XCC_N5P0_M0P30_700, (30, 5) # AL6
yield self.IO_L16N_N5P3_M0P33_700, (32, 6) # AN7
yield self.IO_L16P_N5P2_M0P32_700, (32, 5) # AN6
yield self.IO_L17N_N5P5_M0P35_700, (33, 8) # AP9
yield self.IO_L17P_N5P4_M0P34_700, (32, 8) # AN9
yield self.IO_L18N_XCC_N6P1_M0P37_700, (28, 5) # AJ6
yield self.IO_L18P_XCC_N6P0_M0P36_700, (27, 5) # AH6
yield self.IO_L19N_N6P3_M0P39_700, (29, 9) # AK10
yield self.IO_L19P_N6P2_M0P38_700, (28, 9) # AJ10
yield self.IO_L20N_N6P5_M0P41_700, (28, 7) # AJ8
yield self.IO_L20P_N6P4_M0P40_700, (28, 6) # AJ7
yield self.IO_L21N_XCC_N7P1_M0P43_700, (29, 6) # AK7
yield self.IO_L21P_XCC_N7P0_M0P42_700, (29, 5) # AK6
yield self.IO_L22N_N7P3_M0P45_700, (30, 8) # AL9
yield self.IO_L22P_N7P2_M0P44_700, (29, 8) # AK9
yield self.IO_L23N_N7P5_M0P47_700, (30, 11) # AL12
yield self.IO_L23P_N7P4_M0P46_700, (29, 11) # AK12
yield self.IO_L24N_GC_XCC_N8P1_M0P49_700, (33, 11) # AP12
yield self.IO_L24P_GC_XCC_N8P0_M0P48_700, (32, 11) # AN12
yield self.IO_L25N_N8P3_M0P51_700, (34, 7) # AR8
yield self.IO_L25P_N8P2_M0P50_700, (33, 7) # AP8
yield self.IO_L26N_N8P5_M0P53_700, (33, 6) # AP7
yield self.IO_L26P_N8P4_M0P52_700, (33, 5) # AP6
yield self.IO_VR_700, (28, 11) # AJ12
# Bank 701
yield self.IO_L0N_XCC_N0P1_M0P55_701, (34, 15) # AR16
yield self.IO_L0P_XCC_N0P0_M0P54_701, (34, 14) # AR15
yield self.IO_L1N_N0P3_M0P57_701, (35, 17) # AT18
yield self.IO_L1P_N0P2_M0P56_701, (34, 17) # AR18
yield self.IO_L2N_N0P5_M0P59_701, (34, 20) # AR21
yield self.IO_L2P_N0P4_M0P58_701, (34, 19) # AR20
yield self.IO_L3N_XCC_N1P1_M0P61_701, (36, 16) # AU17
yield self.IO_L3P_XCC_N1P0_M0P60_701, (35, 16) # AT17
yield self.IO_L4N_N1P3_M0P63_701, (35, 15) # AT16
yield self.IO_L4P_N1P2_M0P62_701, (35, 14) # AT15
yield self.IO_L5N_N1P5_M0P65_701, (36, 18) # AU19
yield self.IO_L5P_N1P4_M0P64_701, (36, 17) # AU18
yield self.IO_L6N_GC_XCC_N2P1_M0P67_701, (33, 22) # AP23
yield self.IO_L6P_GC_XCC_N2P0_M0P66_701, (33, 21) # AP22
yield self.IO_L7N_N2P3_M0P69_701, (34, 23) # AR24
yield self.IO_L7P_N2P2_M0P68_701, (34, 22) # AR23
yield self.IO_L8N_N2P5_M0P71_701, (36, 19) # AU20
yield self.IO_L8P_N2P4_M0P70_701, (35, 19) # AT20
yield self.IO_L9N_GC_XCC_N3P1_M0P73_701, (35, 21) # AT22
yield self.IO_L9P_GC_XCC_N3P0_M0P72_701, (35, 20) # AT21
yield self.IO_L10N_N3P3_M0P75_701, (36, 23) # AU24
yield self.IO_L10P_N3P2_M0P74_701, (35, 22) # AT23
yield self.IO_L11N_N3P5_M0P77_701, (36, 22) # AU23
yield self.IO_L11P_N3P4_M0P76_701, (36, 21) # AU22
yield self.IO_L12N_GC_XCC_N4P1_M0P79_701, (29, 15) # AK16
yield self.IO_L12P_GC_XCC_N4P0_M0P78_701, (29, 14) # AK15
yield self.IO_L13N_N4P3_M0P81_701, (29, 18) # AK19
yield self.IO_L13P_N4P2_M0P80_701, (29, 17) # AK18
yield self.IO_L14N_N4P5_M0P83_701, (30, 17) # AL18
yield self.IO_L14P_N4P4_M0P82_701, (30, 16) # AL17
yield self.IO_L15N_XCC_N5P1_M0P85_701, (31, 15) # AM16
yield self.IO_L15P_XCC_N5P0_M0P84_701, (30, 14) # AL15
yield self.IO_L16N_N5P3_M0P87_701, (31, 19) # AM20
yield self.IO_L16P_N5P2_M0P86_701, (31, 18) # AM19
yield self.IO_L17N_N5P5_M0P89_701, (33, 15) # AP16
yield self.IO_L17P_N5P4_M0P88_701, (32, 14) # AN15
yield self.IO_L18N_XCC_N6P1_M0P91_701, (29, 21) # AK22
yield self.IO_L18P_XCC_N6P0_M0P90_701, (29, 20) # AK21
yield self.IO_L19N_N6P3_M0P93_701, (31, 22) # AM23
yield self.IO_L19P_N6P2_M0P92_701, (30, 22) # AL23
yield self.IO_L20N_N6P5_M0P95_701, (30, 20) # AL21
yield self.IO_L20P_N6P4_M0P94_701, (30, 19) # AL20
yield self.IO_L21N_XCC_N7P1_M0P97_701, (32, 21) # AN22
yield self.IO_L21P_XCC_N7P0_M0P96_701, (31, 21) # AM22
yield self.IO_L22N_N7P3_M0P99_701, (33, 20) # AP21
yield self.IO_L22P_N7P2_M0P98_701, (32, 20) # AN21
yield self.IO_L23N_N7P5_M0P101_701, (32, 19) # AN20
yield self.IO_L23P_N7P4_M0P100_701, (32, 18) # AN19
yield self.IO_L24N_GC_XCC_N8P1_M0P103_701, (33, 23) # AP24
yield self.IO_L24P_GC_XCC_N8P0_M0P102_701, (32, 23) # AN24
yield self.IO_L25N_N8P3_M0P105_701, (34, 18) # AR19
yield self.IO_L25P_N8P2_M0P104_701, (33, 18) # AP19
yield self.IO_L26N_N8P5_M0P107_701, (33, 17) # AP18
yield self.IO_L26P_N8P4_M0P106_701, (33, 16) # AP17
# Bank 702
yield self.IO_L0N_XCC_N0P1_M0P109_702, (35, 31) # AT32
yield self.IO_L0P_XCC_N0P0_M0P108_702, (35, 30) # AT31
yield self.IO_L1N_N0P3_M0P111_702, (36, 33) # AU34
yield self.IO_L1P_N0P2_M0P110_702, (35, 32) # AT33
yield self.IO_L2N_N0P5_M0P113_702, (36, 34) # AU35
yield self.IO_L2P_N0P4_M0P112_702, (35, 34) # AT35
yield self.IO_L3N_XCC_N1P1_M0P115_702, (35, 36) # AT37
yield self.IO_L3P_XCC_N1P0_M0P114_702, (35, 35) # AT36
yield self.IO_L4N_N1P3_M0P117_702, (36, 32) # AU33
yield self.IO_L4P_N1P2_M0P116_702, (36, 31) # AU32
yield self.IO_L5N_N1P5_M0P119_702, (36, 27) # AU28
yield self.IO_L5P_N1P4_M0P118_702, (36, 26) # AU27
yield self.IO_L6N_GC_XCC_N2P1_M0P121_702, (34, 33) # AR34
yield self.IO_L6P_GC_XCC_N2P0_M0P120_702, (34, 32) # AR33
yield self.IO_L7N_N2P3_M0P123_702, (34, 35) # AR36
yield self.IO_L7P_N2P2_M0P122_702, (34, 34) # AR35
yield self.IO_L8N_N2P5_M0P125_702, (36, 29) # AU30
yield self.IO_L8P_N2P4_M0P124_702, (35, 29) # AT30
yield self.IO_L9N_GC_XCC_N3P1_M0P127_702, (36, 28) # AU29
yield self.IO_L9P_GC_XCC_N3P0_M0P126_702, (35, 27) # AT28
yield self.IO_L10N_N3P3_M0P129_702, (35, 26) # AT27
yield self.IO_L10P_N3P2_M0P128_702, (35, 25) # AT26
yield self.IO_L11N_N3P5_M0P131_702, (36, 24) # AU25
yield self.IO_L11P_N3P4_M0P130_702, (35, 24) # AT25
yield self.IO_L12N_GC_XCC_N4P1_M0P133_702, (32, 28) # AN29
yield self.IO_L12P_GC_XCC_N4P0_M0P132_702, (31, 27) # AM28
yield self.IO_L13N_N4P3_M0P135_702, (33, 30) # AP31
yield self.IO_L13P_N4P2_M0P134_702, (32, 29) # AN30
yield self.IO_L14N_N4P5_M0P137_702, (33, 26) # AP27
yield self.IO_L14P_N4P4_M0P136_702, (32, 26) # AN27
yield self.IO_L15N_XCC_N5P1_M0P139_702, (33, 25) # AP26
yield self.IO_L15P_XCC_N5P0_M0P138_702, (32, 24) # AN25
yield self.IO_L16N_N5P3_M0P141_702, (33, 28) # AP29
yield self.IO_L16P_N5P2_M0P140_702, (33, 27) # AP28
yield self.IO_L17N_N5P5_M0P143_702, (33, 32) # AP33
yield self.IO_L17P_N5P4_M0P142_702, (33, 31) # AP32
yield self.IO_L18N_XCC_N6P1_M0P145_702, (29, 26) # AK27
yield self.IO_L18P_XCC_N6P0_M0P144_702, (28, 25) # AJ26
yield self.IO_L19N_N6P3_M0P147_702, (29, 27) # AK28
yield self.IO_L19P_N6P2_M0P146_702, (28, 27) # AJ28
yield self.IO_L20N_N6P5_M0P149_702, (29, 24) # AK25
yield self.IO_L20P_N6P4_M0P148_702, (29, 23) # AK24
yield self.IO_L21N_XCC_N7P1_M0P151_702, (31, 24) # AM25
yield self.IO_L21P_XCC_N7P0_M0P150_702, (30, 23) # AL24
yield self.IO_L22N_N7P3_M0P153_702, (30, 26) # AL27
yield self.IO_L22P_N7P2_M0P152_702, (30, 25) # AL26
yield self.IO_L23N_N7P5_M0P155_702, (32, 25) # AN26
yield self.IO_L23P_N7P4_M0P154_702, (31, 25) # AM26
yield self.IO_L24N_GC_XCC_N8P1_M0P157_702, (34, 25) # AR26
yield self.IO_L24P_GC_XCC_N8P0_M0P156_702, (34, 24) # AR25
yield self.IO_L25N_N8P3_M0P159_702, (34, 28) # AR29
yield self.IO_L25P_N8P2_M0P158_702, (34, 27) # AR28
yield self.IO_L26N_N8P5_M0P161_702, (34, 30) # AR31
yield self.IO_L26P_N8P4_M0P160_702, (34, 29) # AR30
# Dedicated / bankless
yield self.GND_SENSE, (7, 13) # H14
yield self.GND_SMON, (17, 15) # V16
yield self.VCCAUX_SMON, (17, 14) # V15
yield self.VCCINT_SENSE, (7, 12) # H13
yield self.VCC_BATT, (22, 10) # AC11
yield self.VCC_FUSE, (24, 10) # AE11
yield self.VN_500, (19, 15) # Y16
yield self.VP_500, (18, 14) # W15
yield self.VREFN_500, (18, 15) # W16
yield self.VREFP_500, (19, 14) # Y15
yield from zip(self.GND, _GND_BALLS, strict=True)
yield from zip(self.GTM_AVCCAUX_L, _GTM_AVCCAUX_L_BALLS, strict=True)
yield from zip(self.GTM_AVCCAUX_RN, _GTM_AVCCAUX_RN_BALLS, strict=True)
yield from zip(self.GTM_AVCC_L, _GTM_AVCC_L_BALLS, strict=True)
yield from zip(self.GTM_AVCC_RN, _GTM_AVCC_RN_BALLS, strict=True)
yield from zip(self.GTM_AVTT_L, _GTM_AVTT_L_BALLS, strict=True)
yield from zip(self.GTM_AVTT_RN, _GTM_AVTT_RN_BALLS, strict=True)
yield from zip(self.GTY_AVCCAUX_RS, _GTY_AVCCAUX_RS_BALLS, strict=True)
yield from zip(self.GTY_AVCC_RS, _GTY_AVCC_RS_BALLS, strict=True)
yield from zip(self.GTY_AVTT_RS, _GTY_AVTT_RS_BALLS, strict=True)
yield from zip(self.NC, _NC_BALLS, strict=True)
yield from zip(self.RSVDGND, _RSVDGND_BALLS, strict=True)
yield from zip(self.VCCAUX, _VCCAUX_BALLS, strict=True)
yield from zip(self.VCCAUX_PMC, _VCCAUX_PMC_BALLS, strict=True)
yield from zip(self.VCCINT, _VCCINT_BALLS, strict=True)
yield from zip(self.VCCINT_GT_L, _VCCINT_GT_L_BALLS, strict=True)
yield from zip(self.VCCINT_GT_R, _VCCINT_GT_R_BALLS, strict=True)
yield from zip(self.VCCO_500, _VCCO_500_BALLS, strict=True)
yield from zip(self.VCCO_501, _VCCO_501_BALLS, strict=True)
yield from zip(self.VCCO_502, _VCCO_502_BALLS, strict=True)
yield from zip(self.VCCO_503, _VCCO_503_BALLS, strict=True)
yield from zip(self.VCCO_700, _VCCO_700_BALLS, strict=True)
yield from zip(self.VCCO_701, _VCCO_701_BALLS, strict=True)
yield from zip(self.VCCO_702, _VCCO_702_BALLS, strict=True)
yield from zip(self.VCC_IO, _VCC_IO_BALLS, strict=True)
yield from zip(self.VCC_PMC, _VCC_PMC_BALLS, strict=True)
yield from zip(self.VCC_PSFP, _VCC_PSFP_BALLS, strict=True)
yield from zip(self.VCC_PSLP, _VCC_PSLP_BALLS, strict=True)
yield from zip(self.VCC_RAM, _VCC_RAM_BALLS, strict=True)
yield from zip(self.VCC_SOC, _VCC_SOC_BALLS, strict=True)
[docs]
def gtm_quad_pins(self) -> dict[int, GTMQuadPins]:
"""Structural lane/refclk pins of each GTM bank."""
return {
202: GTMQuadPins(
rxp=(
self.GTM_RXP0_202,
self.GTM_RXP1_202,
self.GTM_RXP2_202,
self.GTM_RXP3_202,
),
rxn=(
self.GTM_RXN0_202,
self.GTM_RXN1_202,
self.GTM_RXN2_202,
self.GTM_RXN3_202,
),
txp=(
self.GTM_TXP0_202,
self.GTM_TXP1_202,
self.GTM_TXP2_202,
self.GTM_TXP3_202,
),
txn=(
self.GTM_TXN0_202,
self.GTM_TXN1_202,
self.GTM_TXN2_202,
self.GTM_TXN3_202,
),
refclkp=(
self.GTM_REFCLKP0_202,
self.GTM_REFCLKP1_202,
),
refclkn=(
self.GTM_REFCLKN0_202,
self.GTM_REFCLKN1_202,
),
),
203: GTMQuadPins(
rxp=(
self.GTM_RXP0_203,
self.GTM_RXP1_203,
self.GTM_RXP2_203,
self.GTM_RXP3_203,
),
rxn=(
self.GTM_RXN0_203,
self.GTM_RXN1_203,
self.GTM_RXN2_203,
self.GTM_RXN3_203,
),
txp=(
self.GTM_TXP0_203,
self.GTM_TXP1_203,
self.GTM_TXP2_203,
self.GTM_TXP3_203,
),
txn=(
self.GTM_TXN0_203,
self.GTM_TXN1_203,
self.GTM_TXN2_203,
self.GTM_TXN3_203,
),
refclkp=(
self.GTM_REFCLKP0_203,
self.GTM_REFCLKP1_203,
),
refclkn=(
self.GTM_REFCLKN0_203,
self.GTM_REFCLKN1_203,
),
),
204: GTMQuadPins(
rxp=(
self.GTM_RXP0_204,
self.GTM_RXP1_204,
self.GTM_RXP2_204,
self.GTM_RXP3_204,
),
rxn=(
self.GTM_RXN0_204,
self.GTM_RXN1_204,
self.GTM_RXN2_204,
self.GTM_RXN3_204,
),
txp=(
self.GTM_TXP0_204,
self.GTM_TXP1_204,
self.GTM_TXP2_204,
self.GTM_TXP3_204,
),
txn=(
self.GTM_TXN0_204,
self.GTM_TXN1_204,
self.GTM_TXN2_204,
self.GTM_TXN3_204,
),
refclkp=(
self.GTM_REFCLKP0_204,
self.GTM_REFCLKP1_204,
),
refclkn=(
self.GTM_REFCLKN0_204,
self.GTM_REFCLKN1_204,
),
),
205: GTMQuadPins(
rxp=(
self.GTM_RXP0_205,
self.GTM_RXP1_205,
self.GTM_RXP2_205,
self.GTM_RXP3_205,
),
rxn=(
self.GTM_RXN0_205,
self.GTM_RXN1_205,
self.GTM_RXN2_205,
self.GTM_RXN3_205,
),
txp=(
self.GTM_TXP0_205,
self.GTM_TXP1_205,
self.GTM_TXP2_205,
self.GTM_TXP3_205,
),
txn=(
self.GTM_TXN0_205,
self.GTM_TXN1_205,
self.GTM_TXN2_205,
self.GTM_TXN3_205,
),
refclkp=(
self.GTM_REFCLKP0_205,
self.GTM_REFCLKP1_205,
),
refclkn=(
self.GTM_REFCLKN0_205,
self.GTM_REFCLKN1_205,
),
),
206: GTMQuadPins(
rxp=(
self.GTM_RXP0_206,
self.GTM_RXP1_206,
self.GTM_RXP2_206,
self.GTM_RXP3_206,
),
rxn=(
self.GTM_RXN0_206,
self.GTM_RXN1_206,
self.GTM_RXN2_206,
self.GTM_RXN3_206,
),
txp=(
self.GTM_TXP0_206,
self.GTM_TXP1_206,
self.GTM_TXP2_206,
self.GTM_TXP3_206,
),
txn=(
self.GTM_TXN0_206,
self.GTM_TXN1_206,
self.GTM_TXN2_206,
self.GTM_TXN3_206,
),
refclkp=(
self.GTM_REFCLKP0_206,
self.GTM_REFCLKP1_206,
),
refclkn=(
self.GTM_REFCLKN0_206,
self.GTM_REFCLKN1_206,
),
),
207: GTMQuadPins(
rxp=(
self.GTM_RXP0_207,
self.GTM_RXP1_207,
self.GTM_RXP2_207,
self.GTM_RXP3_207,
),
rxn=(
self.GTM_RXN0_207,
self.GTM_RXN1_207,
self.GTM_RXN2_207,
self.GTM_RXN3_207,
),
txp=(
self.GTM_TXP0_207,
self.GTM_TXP1_207,
self.GTM_TXP2_207,
self.GTM_TXP3_207,
),
txn=(
self.GTM_TXN0_207,
self.GTM_TXN1_207,
self.GTM_TXN2_207,
self.GTM_TXN3_207,
),
refclkp=(
self.GTM_REFCLKP0_207,
self.GTM_REFCLKP1_207,
),
refclkn=(
self.GTM_REFCLKN0_207,
self.GTM_REFCLKN1_207,
),
),
}
[docs]
def xpio_triplet_pins(self) -> dict[int, tuple[TripletPin, ...]]:
"""XPIO pins of each DDRMC triplet, keyed by triplet number.
Tuple index ``i`` is pin ``MxPi`` of the pin file: bank ``i // 54``
of the triplet, nibble ``i % 54 // 6``, pin ``i % 6``.
"""
m0 = ( # banks 700/701/702
TripletPin(self.IO_L0P_XCC_N0P0_M0P0_700, DDRMC.YES),
TripletPin(self.IO_L0N_XCC_N0P1_M0P1_700, DDRMC.YES),
TripletPin(self.IO_L1P_N0P2_M0P2_700, DDRMC.YES),
TripletPin(self.IO_L1N_N0P3_M0P3_700, DDRMC.YES),
TripletPin(self.IO_L2P_N0P4_M0P4_700, DDRMC.YES),
TripletPin(self.IO_L2N_N0P5_M0P5_700, DDRMC.YES),
TripletPin(self.IO_L3P_XCC_N1P0_M0P6_700, DDRMC.YES),
TripletPin(self.IO_L3N_XCC_N1P1_M0P7_700, DDRMC.YES),
TripletPin(self.IO_L4P_N1P2_M0P8_700, DDRMC.YES),
TripletPin(self.IO_L4N_N1P3_M0P9_700, DDRMC.YES),
TripletPin(self.IO_L5P_N1P4_M0P10_700, DDRMC.YES),
TripletPin(self.IO_L5N_N1P5_M0P11_700, DDRMC.YES),
TripletPin(self.IO_L6P_GC_XCC_N2P0_M0P12_700, DDRMC.YES_PLUS_GC),
TripletPin(self.IO_L6N_GC_XCC_N2P1_M0P13_700, DDRMC.YES_PLUS_GC),
TripletPin(self.IO_L7P_N2P2_M0P14_700, DDRMC.YES),
TripletPin(self.IO_L7N_N2P3_M0P15_700, DDRMC.YES),
TripletPin(self.IO_L8P_N2P4_M0P16_700, DDRMC.YES),
TripletPin(self.IO_L8N_N2P5_M0P17_700, DDRMC.YES),
TripletPin(self.IO_L9P_GC_XCC_N3P0_M0P18_700, DDRMC.YES_PLUS_GC),
TripletPin(self.IO_L9N_GC_XCC_N3P1_M0P19_700, DDRMC.YES_PLUS_GC),
TripletPin(self.IO_L10P_N3P2_M0P20_700, DDRMC.YES),
TripletPin(self.IO_L10N_N3P3_M0P21_700, DDRMC.YES),
TripletPin(self.IO_L11P_N3P4_M0P22_700, DDRMC.YES),
TripletPin(self.IO_L11N_N3P5_M0P23_700, DDRMC.YES),
TripletPin(self.IO_L12P_GC_XCC_N4P0_M0P24_700, DDRMC.YES_PLUS_GC),
TripletPin(self.IO_L12N_GC_XCC_N4P1_M0P25_700, DDRMC.YES_PLUS_GC),
TripletPin(self.IO_L13P_N4P2_M0P26_700, DDRMC.YES),
TripletPin(self.IO_L13N_N4P3_M0P27_700, DDRMC.YES),
TripletPin(self.IO_L14P_N4P4_M0P28_700, DDRMC.YES),
TripletPin(self.IO_L14N_N4P5_M0P29_700, DDRMC.YES),
TripletPin(self.IO_L15P_XCC_N5P0_M0P30_700, DDRMC.YES),
TripletPin(self.IO_L15N_XCC_N5P1_M0P31_700, DDRMC.YES),
TripletPin(self.IO_L16P_N5P2_M0P32_700, DDRMC.YES),
TripletPin(self.IO_L16N_N5P3_M0P33_700, DDRMC.YES),
TripletPin(self.IO_L17P_N5P4_M0P34_700, DDRMC.YES),
TripletPin(self.IO_L17N_N5P5_M0P35_700, DDRMC.YES),
TripletPin(self.IO_L18P_XCC_N6P0_M0P36_700, DDRMC.YES),
TripletPin(self.IO_L18N_XCC_N6P1_M0P37_700, DDRMC.YES),
TripletPin(self.IO_L19P_N6P2_M0P38_700, DDRMC.YES),
TripletPin(self.IO_L19N_N6P3_M0P39_700, DDRMC.YES),
TripletPin(self.IO_L20P_N6P4_M0P40_700, DDRMC.YES),
TripletPin(self.IO_L20N_N6P5_M0P41_700, DDRMC.YES),
TripletPin(self.IO_L21P_XCC_N7P0_M0P42_700, DDRMC.YES),
TripletPin(self.IO_L21N_XCC_N7P1_M0P43_700, DDRMC.YES),
TripletPin(self.IO_L22P_N7P2_M0P44_700, DDRMC.YES),
TripletPin(self.IO_L22N_N7P3_M0P45_700, DDRMC.YES),
TripletPin(self.IO_L23P_N7P4_M0P46_700, DDRMC.YES),
TripletPin(self.IO_L23N_N7P5_M0P47_700, DDRMC.YES),
TripletPin(self.IO_L24P_GC_XCC_N8P0_M0P48_700, DDRMC.YES_PLUS_GC),
TripletPin(self.IO_L24N_GC_XCC_N8P1_M0P49_700, DDRMC.YES_PLUS_GC),
TripletPin(self.IO_L25P_N8P2_M0P50_700, DDRMC.YES),
TripletPin(self.IO_L25N_N8P3_M0P51_700, DDRMC.YES),
TripletPin(self.IO_L26P_N8P4_M0P52_700, DDRMC.YES),
TripletPin(self.IO_L26N_N8P5_M0P53_700, DDRMC.YES),
TripletPin(self.IO_L0P_XCC_N0P0_M0P54_701, DDRMC.YES),
TripletPin(self.IO_L0N_XCC_N0P1_M0P55_701, DDRMC.YES),
TripletPin(self.IO_L1P_N0P2_M0P56_701, DDRMC.YES),
TripletPin(self.IO_L1N_N0P3_M0P57_701, DDRMC.YES),
TripletPin(self.IO_L2P_N0P4_M0P58_701, DDRMC.YES),
TripletPin(self.IO_L2N_N0P5_M0P59_701, DDRMC.YES),
TripletPin(self.IO_L3P_XCC_N1P0_M0P60_701, DDRMC.YES),
TripletPin(self.IO_L3N_XCC_N1P1_M0P61_701, DDRMC.YES),
TripletPin(self.IO_L4P_N1P2_M0P62_701, DDRMC.YES),
TripletPin(self.IO_L4N_N1P3_M0P63_701, DDRMC.YES),
TripletPin(self.IO_L5P_N1P4_M0P64_701, DDRMC.YES),
TripletPin(self.IO_L5N_N1P5_M0P65_701, DDRMC.YES),
TripletPin(self.IO_L6P_GC_XCC_N2P0_M0P66_701, DDRMC.YES_PLUS_GC),
TripletPin(self.IO_L6N_GC_XCC_N2P1_M0P67_701, DDRMC.YES_PLUS_GC),
TripletPin(self.IO_L7P_N2P2_M0P68_701, DDRMC.YES),
TripletPin(self.IO_L7N_N2P3_M0P69_701, DDRMC.YES),
TripletPin(self.IO_L8P_N2P4_M0P70_701, DDRMC.YES),
TripletPin(self.IO_L8N_N2P5_M0P71_701, DDRMC.YES),
TripletPin(self.IO_L9P_GC_XCC_N3P0_M0P72_701, DDRMC.YES_PLUS_GC),
TripletPin(self.IO_L9N_GC_XCC_N3P1_M0P73_701, DDRMC.YES_PLUS_GC),
TripletPin(self.IO_L10P_N3P2_M0P74_701, DDRMC.YES),
TripletPin(self.IO_L10N_N3P3_M0P75_701, DDRMC.YES),
TripletPin(self.IO_L11P_N3P4_M0P76_701, DDRMC.YES),
TripletPin(self.IO_L11N_N3P5_M0P77_701, DDRMC.YES),
TripletPin(self.IO_L12P_GC_XCC_N4P0_M0P78_701, DDRMC.YES_PLUS_GC),
TripletPin(self.IO_L12N_GC_XCC_N4P1_M0P79_701, DDRMC.YES_PLUS_GC),
TripletPin(self.IO_L13P_N4P2_M0P80_701, DDRMC.YES),
TripletPin(self.IO_L13N_N4P3_M0P81_701, DDRMC.YES),
TripletPin(self.IO_L14P_N4P4_M0P82_701, DDRMC.YES),
TripletPin(self.IO_L14N_N4P5_M0P83_701, DDRMC.YES),
TripletPin(self.IO_L15P_XCC_N5P0_M0P84_701, DDRMC.YES),
TripletPin(self.IO_L15N_XCC_N5P1_M0P85_701, DDRMC.YES),
TripletPin(self.IO_L16P_N5P2_M0P86_701, DDRMC.YES),
TripletPin(self.IO_L16N_N5P3_M0P87_701, DDRMC.YES),
TripletPin(self.IO_L17P_N5P4_M0P88_701, DDRMC.YES),
TripletPin(self.IO_L17N_N5P5_M0P89_701, DDRMC.YES),
TripletPin(self.IO_L18P_XCC_N6P0_M0P90_701, DDRMC.YES),
TripletPin(self.IO_L18N_XCC_N6P1_M0P91_701, DDRMC.YES),
TripletPin(self.IO_L19P_N6P2_M0P92_701, DDRMC.YES),
TripletPin(self.IO_L19N_N6P3_M0P93_701, DDRMC.YES),
TripletPin(self.IO_L20P_N6P4_M0P94_701, DDRMC.YES),
TripletPin(self.IO_L20N_N6P5_M0P95_701, DDRMC.YES),
TripletPin(self.IO_L21P_XCC_N7P0_M0P96_701, DDRMC.YES),
TripletPin(self.IO_L21N_XCC_N7P1_M0P97_701, DDRMC.YES),
TripletPin(self.IO_L22P_N7P2_M0P98_701, DDRMC.YES),
TripletPin(self.IO_L22N_N7P3_M0P99_701, DDRMC.YES),
TripletPin(self.IO_L23P_N7P4_M0P100_701, DDRMC.YES),
TripletPin(self.IO_L23N_N7P5_M0P101_701, DDRMC.YES),
TripletPin(self.IO_L24P_GC_XCC_N8P0_M0P102_701, DDRMC.YES_PLUS_GC),
TripletPin(self.IO_L24N_GC_XCC_N8P1_M0P103_701, DDRMC.YES_PLUS_GC),
TripletPin(self.IO_L25P_N8P2_M0P104_701, DDRMC.YES),
TripletPin(self.IO_L25N_N8P3_M0P105_701, DDRMC.YES),
TripletPin(self.IO_L26P_N8P4_M0P106_701, DDRMC.YES),
TripletPin(self.IO_L26N_N8P5_M0P107_701, DDRMC.YES),
TripletPin(self.IO_L0P_XCC_N0P0_M0P108_702, DDRMC.YES),
TripletPin(self.IO_L0N_XCC_N0P1_M0P109_702, DDRMC.YES),
TripletPin(self.IO_L1P_N0P2_M0P110_702, DDRMC.YES),
TripletPin(self.IO_L1N_N0P3_M0P111_702, DDRMC.YES),
TripletPin(self.IO_L2P_N0P4_M0P112_702, DDRMC.YES),
TripletPin(self.IO_L2N_N0P5_M0P113_702, DDRMC.YES),
TripletPin(self.IO_L3P_XCC_N1P0_M0P114_702, DDRMC.YES),
TripletPin(self.IO_L3N_XCC_N1P1_M0P115_702, DDRMC.YES),
TripletPin(self.IO_L4P_N1P2_M0P116_702, DDRMC.YES),
TripletPin(self.IO_L4N_N1P3_M0P117_702, DDRMC.YES),
TripletPin(self.IO_L5P_N1P4_M0P118_702, DDRMC.YES),
TripletPin(self.IO_L5N_N1P5_M0P119_702, DDRMC.YES),
TripletPin(self.IO_L6P_GC_XCC_N2P0_M0P120_702, DDRMC.YES_PLUS_GC),
TripletPin(self.IO_L6N_GC_XCC_N2P1_M0P121_702, DDRMC.YES_PLUS_GC),
TripletPin(self.IO_L7P_N2P2_M0P122_702, DDRMC.YES),
TripletPin(self.IO_L7N_N2P3_M0P123_702, DDRMC.YES),
TripletPin(self.IO_L8P_N2P4_M0P124_702, DDRMC.YES),
TripletPin(self.IO_L8N_N2P5_M0P125_702, DDRMC.YES),
TripletPin(self.IO_L9P_GC_XCC_N3P0_M0P126_702, DDRMC.YES_PLUS_GC),
TripletPin(self.IO_L9N_GC_XCC_N3P1_M0P127_702, DDRMC.YES_PLUS_GC),
TripletPin(self.IO_L10P_N3P2_M0P128_702, DDRMC.YES),
TripletPin(self.IO_L10N_N3P3_M0P129_702, DDRMC.YES),
TripletPin(self.IO_L11P_N3P4_M0P130_702, DDRMC.YES),
TripletPin(self.IO_L11N_N3P5_M0P131_702, DDRMC.YES),
TripletPin(self.IO_L12P_GC_XCC_N4P0_M0P132_702, DDRMC.NO),
TripletPin(self.IO_L12N_GC_XCC_N4P1_M0P133_702, DDRMC.NO),
TripletPin(self.IO_L13P_N4P2_M0P134_702, DDRMC.NO),
TripletPin(self.IO_L13N_N4P3_M0P135_702, DDRMC.NO),
TripletPin(self.IO_L14P_N4P4_M0P136_702, DDRMC.NO),
TripletPin(self.IO_L14N_N4P5_M0P137_702, DDRMC.NO),
TripletPin(self.IO_L15P_XCC_N5P0_M0P138_702, DDRMC.NO),
TripletPin(self.IO_L15N_XCC_N5P1_M0P139_702, DDRMC.NO),
TripletPin(self.IO_L16P_N5P2_M0P140_702, DDRMC.NO),
TripletPin(self.IO_L16N_N5P3_M0P141_702, DDRMC.NO),
TripletPin(self.IO_L17P_N5P4_M0P142_702, DDRMC.NO),
TripletPin(self.IO_L17N_N5P5_M0P143_702, DDRMC.NO),
TripletPin(self.IO_L18P_XCC_N6P0_M0P144_702, DDRMC.NO),
TripletPin(self.IO_L18N_XCC_N6P1_M0P145_702, DDRMC.NO),
TripletPin(self.IO_L19P_N6P2_M0P146_702, DDRMC.NO),
TripletPin(self.IO_L19N_N6P3_M0P147_702, DDRMC.NO),
TripletPin(self.IO_L20P_N6P4_M0P148_702, DDRMC.NO),
TripletPin(self.IO_L20N_N6P5_M0P149_702, DDRMC.NO),
TripletPin(self.IO_L21P_XCC_N7P0_M0P150_702, DDRMC.NO),
TripletPin(self.IO_L21N_XCC_N7P1_M0P151_702, DDRMC.NO),
TripletPin(self.IO_L22P_N7P2_M0P152_702, DDRMC.NO),
TripletPin(self.IO_L22N_N7P3_M0P153_702, DDRMC.NO),
TripletPin(self.IO_L23P_N7P4_M0P154_702, DDRMC.NO),
TripletPin(self.IO_L23N_N7P5_M0P155_702, DDRMC.NO),
TripletPin(self.IO_L24P_GC_XCC_N8P0_M0P156_702, DDRMC.YES_PLUS_GC),
TripletPin(self.IO_L24N_GC_XCC_N8P1_M0P157_702, DDRMC.YES_PLUS_GC),
TripletPin(self.IO_L25P_N8P2_M0P158_702, DDRMC.YES),
TripletPin(self.IO_L25N_N8P3_M0P159_702, DDRMC.YES),
TripletPin(self.IO_L26P_N8P4_M0P160_702, DDRMC.YES),
TripletPin(self.IO_L26N_N8P5_M0P161_702, DDRMC.YES),
)
return {0: m0}
[docs]
def symbol_partitions(self) -> Iterator[SymbolPartition]:
"""Yield the schematic box partitions (see .symbols)."""
# Bank 103 (GTY)
yield SymbolPartition(
left=(
self.GTY_RXN0_103,
self.GTY_RXN1_103,
self.GTY_RXN2_103,
self.GTY_RXN3_103,
self.GTY_RXP0_103,
self.GTY_RXP1_103,
self.GTY_RXP2_103,
self.GTY_RXP3_103,
),
right=(
self.GTY_TXN0_103,
self.GTY_TXN1_103,
self.GTY_TXN2_103,
self.GTY_TXN3_103,
self.GTY_TXP0_103,
self.GTY_TXP1_103,
self.GTY_TXP2_103,
self.GTY_TXP3_103,
self.GTY_REFCLKN0_103,
self.GTY_REFCLKN1_103,
self.GTY_REFCLKP0_103,
self.GTY_REFCLKP1_103,
),
)
# Bank 105 (GTY)
yield SymbolPartition(
left=(
self.GTY_RXN0_105,
self.GTY_RXN1_105,
self.GTY_RXN2_105,
self.GTY_RXN3_105,
self.GTY_RXP0_105,
self.GTY_RXP1_105,
self.GTY_RXP2_105,
self.GTY_RXP3_105,
),
right=(
self.GTY_TXN0_105,
self.GTY_TXN1_105,
self.GTY_TXN2_105,
self.GTY_TXN3_105,
self.GTY_TXP0_105,
self.GTY_TXP1_105,
self.GTY_TXP2_105,
self.GTY_TXP3_105,
self.GTY_REFCLKN0_105,
self.GTY_REFCLKN1_105,
self.GTY_REFCLKP0_105,
self.GTY_REFCLKP1_105,
),
down=(
self.GTY_AVTTRCAL_RS,
self.GTY_RREF_RS,
),
)
# Bank 109 (GTM)
yield SymbolPartition(
down=(
self.GTM_AVTTRCAL_RN,
self.GTM_RREF_RN,
),
)
# Bank 202 (GTM)
yield SymbolPartition(
left=(
self.GTM_RXN0_202,
self.GTM_RXN1_202,
self.GTM_RXN2_202,
self.GTM_RXN3_202,
self.GTM_RXP0_202,
self.GTM_RXP1_202,
self.GTM_RXP2_202,
self.GTM_RXP3_202,
),
right=(
self.GTM_TXN0_202,
self.GTM_TXN1_202,
self.GTM_TXN2_202,
self.GTM_TXN3_202,
self.GTM_TXP0_202,
self.GTM_TXP1_202,
self.GTM_TXP2_202,
self.GTM_TXP3_202,
self.GTM_REFCLKN0_202,
self.GTM_REFCLKN1_202,
self.GTM_REFCLKP0_202,
self.GTM_REFCLKP1_202,
),
)
# Bank 203 (GTM)
yield SymbolPartition(
left=(
self.GTM_RXN0_203,
self.GTM_RXN1_203,
self.GTM_RXN2_203,
self.GTM_RXN3_203,
self.GTM_RXP0_203,
self.GTM_RXP1_203,
self.GTM_RXP2_203,
self.GTM_RXP3_203,
),
right=(
self.GTM_TXN0_203,
self.GTM_TXN1_203,
self.GTM_TXN2_203,
self.GTM_TXN3_203,
self.GTM_TXP0_203,
self.GTM_TXP1_203,
self.GTM_TXP2_203,
self.GTM_TXP3_203,
self.GTM_REFCLKN0_203,
self.GTM_REFCLKN1_203,
self.GTM_REFCLKP0_203,
self.GTM_REFCLKP1_203,
),
down=(
self.GTM_AVTTRCAL_L,
self.GTM_RREF_L,
),
)
# Bank 204 (GTM)
yield SymbolPartition(
left=(
self.GTM_RXN0_204,
self.GTM_RXN1_204,
self.GTM_RXN2_204,
self.GTM_RXN3_204,
self.GTM_RXP0_204,
self.GTM_RXP1_204,
self.GTM_RXP2_204,
self.GTM_RXP3_204,
),
right=(
self.GTM_TXN0_204,
self.GTM_TXN1_204,
self.GTM_TXN2_204,
self.GTM_TXN3_204,
self.GTM_TXP0_204,
self.GTM_TXP1_204,
self.GTM_TXP2_204,
self.GTM_TXP3_204,
self.GTM_REFCLKN0_204,
self.GTM_REFCLKN1_204,
self.GTM_REFCLKP0_204,
self.GTM_REFCLKP1_204,
),
)
# Bank 205 (GTM)
yield SymbolPartition(
left=(
self.GTM_RXN0_205,
self.GTM_RXN1_205,
self.GTM_RXN2_205,
self.GTM_RXN3_205,
self.GTM_RXP0_205,
self.GTM_RXP1_205,
self.GTM_RXP2_205,
self.GTM_RXP3_205,
),
right=(
self.GTM_TXN0_205,
self.GTM_TXN1_205,
self.GTM_TXN2_205,
self.GTM_TXN3_205,
self.GTM_TXP0_205,
self.GTM_TXP1_205,
self.GTM_TXP2_205,
self.GTM_TXP3_205,
self.GTM_REFCLKN0_205,
self.GTM_REFCLKN1_205,
self.GTM_REFCLKP0_205,
self.GTM_REFCLKP1_205,
),
)
# Bank 206 (GTM)
yield SymbolPartition(
left=(
self.GTM_RXN0_206,
self.GTM_RXN1_206,
self.GTM_RXN2_206,
self.GTM_RXN3_206,
self.GTM_RXP0_206,
self.GTM_RXP1_206,
self.GTM_RXP2_206,
self.GTM_RXP3_206,
),
right=(
self.GTM_TXN0_206,
self.GTM_TXN1_206,
self.GTM_TXN2_206,
self.GTM_TXN3_206,
self.GTM_TXP0_206,
self.GTM_TXP1_206,
self.GTM_TXP2_206,
self.GTM_TXP3_206,
self.GTM_REFCLKN0_206,
self.GTM_REFCLKN1_206,
self.GTM_REFCLKP0_206,
self.GTM_REFCLKP1_206,
),
)
# Bank 207 (GTM)
yield SymbolPartition(
left=(
self.GTM_RXN0_207,
self.GTM_RXN1_207,
self.GTM_RXN2_207,
self.GTM_RXN3_207,
self.GTM_RXP0_207,
self.GTM_RXP1_207,
self.GTM_RXP2_207,
self.GTM_RXP3_207,
),
right=(
self.GTM_TXN0_207,
self.GTM_TXN1_207,
self.GTM_TXN2_207,
self.GTM_TXN3_207,
self.GTM_TXP0_207,
self.GTM_TXP1_207,
self.GTM_TXP2_207,
self.GTM_TXP3_207,
self.GTM_REFCLKN0_207,
self.GTM_REFCLKN1_207,
self.GTM_REFCLKP0_207,
self.GTM_REFCLKP1_207,
),
)
# Bank 500 (PMCMIO)
yield SymbolPartition(
left=(
self.PMC_MIO0_500,
self.PMC_MIO1_500,
self.PMC_MIO2_500,
self.PMC_MIO3_500,
self.PMC_MIO4_500,
self.PMC_MIO5_500,
self.PMC_MIO6_500,
self.PMC_MIO7_500,
self.PMC_MIO8_500,
self.PMC_MIO9_500,
self.PMC_MIO10_500,
self.PMC_MIO11_500,
self.PMC_MIO12_500,
),
right=(
self.PMC_MIO13_500,
self.PMC_MIO14_500,
self.PMC_MIO15_500,
self.PMC_MIO16_500,
self.PMC_MIO17_500,
self.PMC_MIO18_500,
self.PMC_MIO19_500,
self.PMC_MIO20_500,
self.PMC_MIO21_500,
self.PMC_MIO22_500,
self.PMC_MIO23_500,
self.PMC_MIO24_500,
self.PMC_MIO25_500,
),
down=(*self.VCCO_500,),
)
# Bank 501 (PMCMIO)
yield SymbolPartition(
left=(
self.PMC_MIO26_501,
self.PMC_MIO27_501,
self.PMC_MIO28_501,
self.PMC_MIO29_501,
self.PMC_MIO30_501,
self.PMC_MIO31_501,
self.PMC_MIO32_501,
self.PMC_MIO33_501,
self.PMC_MIO34_501,
self.PMC_MIO35_501,
self.PMC_MIO36_501,
self.PMC_MIO37_501,
self.PMC_MIO38_501,
),
right=(
self.PMC_MIO39_501,
self.PMC_MIO40_501,
self.PMC_MIO41_501,
self.PMC_MIO42_501,
self.PMC_MIO43_501,
self.PMC_MIO44_501,
self.PMC_MIO45_501,
self.PMC_MIO46_501,
self.PMC_MIO47_501,
self.PMC_MIO48_501,
self.PMC_MIO49_501,
self.PMC_MIO50_501,
self.PMC_MIO51_501,
),
down=(*self.VCCO_501,),
)
# Bank 502 (LPDMIO)
yield SymbolPartition(
left=(
self.LPD_MIO0_502,
self.LPD_MIO1_502,
self.LPD_MIO2_502,
self.LPD_MIO3_502,
self.LPD_MIO4_502,
self.LPD_MIO5_502,
self.LPD_MIO6_502,
self.LPD_MIO7_502,
self.LPD_MIO8_502,
self.LPD_MIO9_502,
self.LPD_MIO10_502,
self.LPD_MIO11_502,
self.LPD_MIO12_502,
),
right=(
self.LPD_MIO13_502,
self.LPD_MIO14_502,
self.LPD_MIO15_502,
self.LPD_MIO16_502,
self.LPD_MIO17_502,
self.LPD_MIO18_502,
self.LPD_MIO19_502,
self.LPD_MIO20_502,
self.LPD_MIO21_502,
self.LPD_MIO22_502,
self.LPD_MIO23_502,
self.LPD_MIO24_502,
self.LPD_MIO25_502,
),
down=(*self.VCCO_502,),
)
# Bank 503 (PMCDIO)
yield SymbolPartition(
left=(
self.DONE_503,
self.ERROR_OUT_503,
self.MODE0_503,
self.MODE1_503,
self.MODE2_503,
self.MODE3_503,
self.POR_B_503,
self.PUDC_B_503,
),
right=(
self.REF_CLK_503,
self.RTC_PADI_503,
self.RTC_PADO_503,
self.TCK_503,
self.TDI_503,
self.TDO_503,
self.TMS_503,
),
down=(*self.VCCO_503,),
)
# Bank 700 (XPIO)
yield SymbolPartition(
left=(
self.IO_L0N_XCC_N0P1_M0P1_700,
self.IO_L0P_XCC_N0P0_M0P0_700,
self.IO_L1N_N0P3_M0P3_700,
self.IO_L1P_N0P2_M0P2_700,
self.IO_L2N_N0P5_M0P5_700,
self.IO_L2P_N0P4_M0P4_700,
self.IO_L3N_XCC_N1P1_M0P7_700,
self.IO_L3P_XCC_N1P0_M0P6_700,
self.IO_L4N_N1P3_M0P9_700,
self.IO_L4P_N1P2_M0P8_700,
self.IO_L5N_N1P5_M0P11_700,
self.IO_L5P_N1P4_M0P10_700,
self.IO_L6N_GC_XCC_N2P1_M0P13_700,
self.IO_L6P_GC_XCC_N2P0_M0P12_700,
self.IO_L7N_N2P3_M0P15_700,
self.IO_L7P_N2P2_M0P14_700,
self.IO_L8N_N2P5_M0P17_700,
self.IO_L8P_N2P4_M0P16_700,
self.IO_L9N_GC_XCC_N3P1_M0P19_700,
self.IO_L9P_GC_XCC_N3P0_M0P18_700,
self.IO_L10N_N3P3_M0P21_700,
self.IO_L10P_N3P2_M0P20_700,
self.IO_L11N_N3P5_M0P23_700,
self.IO_L11P_N3P4_M0P22_700,
self.IO_L12N_GC_XCC_N4P1_M0P25_700,
self.IO_L12P_GC_XCC_N4P0_M0P24_700,
self.IO_L13N_N4P3_M0P27_700,
self.IO_L13P_N4P2_M0P26_700,
),
right=(
self.IO_L14N_N4P5_M0P29_700,
self.IO_L14P_N4P4_M0P28_700,
self.IO_L15N_XCC_N5P1_M0P31_700,
self.IO_L15P_XCC_N5P0_M0P30_700,
self.IO_L16N_N5P3_M0P33_700,
self.IO_L16P_N5P2_M0P32_700,
self.IO_L17N_N5P5_M0P35_700,
self.IO_L17P_N5P4_M0P34_700,
self.IO_L18N_XCC_N6P1_M0P37_700,
self.IO_L18P_XCC_N6P0_M0P36_700,
self.IO_L19N_N6P3_M0P39_700,
self.IO_L19P_N6P2_M0P38_700,
self.IO_L20N_N6P5_M0P41_700,
self.IO_L20P_N6P4_M0P40_700,
self.IO_L21N_XCC_N7P1_M0P43_700,
self.IO_L21P_XCC_N7P0_M0P42_700,
self.IO_L22N_N7P3_M0P45_700,
self.IO_L22P_N7P2_M0P44_700,
self.IO_L23N_N7P5_M0P47_700,
self.IO_L23P_N7P4_M0P46_700,
self.IO_L24N_GC_XCC_N8P1_M0P49_700,
self.IO_L24P_GC_XCC_N8P0_M0P48_700,
self.IO_L25N_N8P3_M0P51_700,
self.IO_L25P_N8P2_M0P50_700,
self.IO_L26N_N8P5_M0P53_700,
self.IO_L26P_N8P4_M0P52_700,
self.IO_VR_700,
),
down=(*self.VCCO_700,),
)
# Bank 701 (XPIO)
yield SymbolPartition(
left=(
self.IO_L0N_XCC_N0P1_M0P55_701,
self.IO_L0P_XCC_N0P0_M0P54_701,
self.IO_L1N_N0P3_M0P57_701,
self.IO_L1P_N0P2_M0P56_701,
self.IO_L2N_N0P5_M0P59_701,
self.IO_L2P_N0P4_M0P58_701,
self.IO_L3N_XCC_N1P1_M0P61_701,
self.IO_L3P_XCC_N1P0_M0P60_701,
self.IO_L4N_N1P3_M0P63_701,
self.IO_L4P_N1P2_M0P62_701,
self.IO_L5N_N1P5_M0P65_701,
self.IO_L5P_N1P4_M0P64_701,
self.IO_L6N_GC_XCC_N2P1_M0P67_701,
self.IO_L6P_GC_XCC_N2P0_M0P66_701,
self.IO_L7N_N2P3_M0P69_701,
self.IO_L7P_N2P2_M0P68_701,
self.IO_L8N_N2P5_M0P71_701,
self.IO_L8P_N2P4_M0P70_701,
self.IO_L9N_GC_XCC_N3P1_M0P73_701,
self.IO_L9P_GC_XCC_N3P0_M0P72_701,
self.IO_L10N_N3P3_M0P75_701,
self.IO_L10P_N3P2_M0P74_701,
self.IO_L11N_N3P5_M0P77_701,
self.IO_L11P_N3P4_M0P76_701,
self.IO_L12N_GC_XCC_N4P1_M0P79_701,
self.IO_L12P_GC_XCC_N4P0_M0P78_701,
self.IO_L13N_N4P3_M0P81_701,
),
right=(
self.IO_L13P_N4P2_M0P80_701,
self.IO_L14N_N4P5_M0P83_701,
self.IO_L14P_N4P4_M0P82_701,
self.IO_L15N_XCC_N5P1_M0P85_701,
self.IO_L15P_XCC_N5P0_M0P84_701,
self.IO_L16N_N5P3_M0P87_701,
self.IO_L16P_N5P2_M0P86_701,
self.IO_L17N_N5P5_M0P89_701,
self.IO_L17P_N5P4_M0P88_701,
self.IO_L18N_XCC_N6P1_M0P91_701,
self.IO_L18P_XCC_N6P0_M0P90_701,
self.IO_L19N_N6P3_M0P93_701,
self.IO_L19P_N6P2_M0P92_701,
self.IO_L20N_N6P5_M0P95_701,
self.IO_L20P_N6P4_M0P94_701,
self.IO_L21N_XCC_N7P1_M0P97_701,
self.IO_L21P_XCC_N7P0_M0P96_701,
self.IO_L22N_N7P3_M0P99_701,
self.IO_L22P_N7P2_M0P98_701,
self.IO_L23N_N7P5_M0P101_701,
self.IO_L23P_N7P4_M0P100_701,
self.IO_L24N_GC_XCC_N8P1_M0P103_701,
self.IO_L24P_GC_XCC_N8P0_M0P102_701,
self.IO_L25N_N8P3_M0P105_701,
self.IO_L25P_N8P2_M0P104_701,
self.IO_L26N_N8P5_M0P107_701,
self.IO_L26P_N8P4_M0P106_701,
),
down=(*self.VCCO_701,),
)
# Bank 702 (XPIO)
yield SymbolPartition(
left=(
self.IO_L0N_XCC_N0P1_M0P109_702,
self.IO_L0P_XCC_N0P0_M0P108_702,
self.IO_L1N_N0P3_M0P111_702,
self.IO_L1P_N0P2_M0P110_702,
self.IO_L2N_N0P5_M0P113_702,
self.IO_L2P_N0P4_M0P112_702,
self.IO_L3N_XCC_N1P1_M0P115_702,
self.IO_L3P_XCC_N1P0_M0P114_702,
self.IO_L4N_N1P3_M0P117_702,
self.IO_L4P_N1P2_M0P116_702,
self.IO_L5N_N1P5_M0P119_702,
self.IO_L5P_N1P4_M0P118_702,
self.IO_L6N_GC_XCC_N2P1_M0P121_702,
self.IO_L6P_GC_XCC_N2P0_M0P120_702,
self.IO_L7N_N2P3_M0P123_702,
self.IO_L7P_N2P2_M0P122_702,
self.IO_L8N_N2P5_M0P125_702,
self.IO_L8P_N2P4_M0P124_702,
self.IO_L9N_GC_XCC_N3P1_M0P127_702,
self.IO_L9P_GC_XCC_N3P0_M0P126_702,
self.IO_L10N_N3P3_M0P129_702,
self.IO_L10P_N3P2_M0P128_702,
self.IO_L11N_N3P5_M0P131_702,
self.IO_L11P_N3P4_M0P130_702,
self.IO_L12N_GC_XCC_N4P1_M0P133_702,
self.IO_L12P_GC_XCC_N4P0_M0P132_702,
self.IO_L13N_N4P3_M0P135_702,
),
right=(
self.IO_L13P_N4P2_M0P134_702,
self.IO_L14N_N4P5_M0P137_702,
self.IO_L14P_N4P4_M0P136_702,
self.IO_L15N_XCC_N5P1_M0P139_702,
self.IO_L15P_XCC_N5P0_M0P138_702,
self.IO_L16N_N5P3_M0P141_702,
self.IO_L16P_N5P2_M0P140_702,
self.IO_L17N_N5P5_M0P143_702,
self.IO_L17P_N5P4_M0P142_702,
self.IO_L18N_XCC_N6P1_M0P145_702,
self.IO_L18P_XCC_N6P0_M0P144_702,
self.IO_L19N_N6P3_M0P147_702,
self.IO_L19P_N6P2_M0P146_702,
self.IO_L20N_N6P5_M0P149_702,
self.IO_L20P_N6P4_M0P148_702,
self.IO_L21N_XCC_N7P1_M0P151_702,
self.IO_L21P_XCC_N7P0_M0P150_702,
self.IO_L22N_N7P3_M0P153_702,
self.IO_L22P_N7P2_M0P152_702,
self.IO_L23N_N7P5_M0P155_702,
self.IO_L23P_N7P4_M0P154_702,
self.IO_L24N_GC_XCC_N8P1_M0P157_702,
self.IO_L24P_GC_XCC_N8P0_M0P156_702,
self.IO_L25N_N8P3_M0P159_702,
self.IO_L25P_N8P2_M0P158_702,
self.IO_L26N_N8P5_M0P161_702,
self.IO_L26P_N8P4_M0P160_702,
),
down=(*self.VCCO_702,),
)
# Dedicated / analog singletons
yield SymbolPartition(
left=(
self.GND_SENSE,
self.GND_SMON,
self.VCCAUX_SMON,
self.VCCINT_SENSE,
self.VCC_BATT,
),
right=(
self.VCC_FUSE,
self.VN_500,
self.VP_500,
self.VREFN_500,
self.VREFP_500,
),
)
# Power/ground: GND[0:64]
yield SymbolPartition(
left=(*self.GND[0:32],),
right=(*self.GND[32:64],),
)
# Power/ground: GND[64:128]
yield SymbolPartition(
left=(*self.GND[64:96],),
right=(*self.GND[96:128],),
)
# Power/ground: GND[128:192]
yield SymbolPartition(
left=(*self.GND[128:160],),
right=(*self.GND[160:192],),
)
# Power/ground: GND[192:256]
yield SymbolPartition(
left=(*self.GND[192:224],),
right=(*self.GND[224:256],),
)
# Power/ground: GND[256:320]
yield SymbolPartition(
left=(*self.GND[256:288],),
right=(*self.GND[288:320],),
)
# Power/ground: GND[320:384]
yield SymbolPartition(
left=(*self.GND[320:352],),
right=(*self.GND[352:384],),
)
# Power/ground: GND[384:448]
yield SymbolPartition(
left=(*self.GND[384:416],),
right=(*self.GND[416:448],),
)
# Power/ground: GND[448:512]
yield SymbolPartition(
left=(*self.GND[448:480],),
right=(*self.GND[480:512],),
)
# Power/ground: GND[512:576]
yield SymbolPartition(
left=(*self.GND[512:544],),
right=(*self.GND[544:576],),
)
# Power/ground: GND[576:640]
yield SymbolPartition(
left=(*self.GND[576:608],),
right=(*self.GND[608:640],),
)
# Power/ground: GND[640:689]
yield SymbolPartition(
left=(*self.GND[640:665],),
right=(*self.GND[665:689],),
)
# Power/ground: VCCINT[0:64]
yield SymbolPartition(
left=(*self.VCCINT[0:32],),
right=(*self.VCCINT[32:64],),
)
# Power/ground: VCCINT[64:84]
yield SymbolPartition(
left=(*self.VCCINT[64:74],),
right=(*self.VCCINT[74:84],),
)
# Power/ground: NC
yield SymbolPartition(
left=(*self.NC[0:30],),
right=(*self.NC[30:60],),
)
# Power/ground: VCC_SOC, GTM_AVTT_L, GTM_AVCC_L, VCCAUX, VCC_RAM, VCCINT_GT_L, GTM_AVTT_RN, GTY_AVTT_RS, VCC_PSFP, GTM_AVCC_RN
yield SymbolPartition(
left=(
*self.VCC_SOC,
*self.GTM_AVTT_L,
*self.GTM_AVCC_L,
),
right=(
*self.VCCAUX,
*self.VCC_RAM,
*self.VCCINT_GT_L,
*self.GTM_AVTT_RN,
*self.GTY_AVTT_RS,
*self.VCC_PSFP,
*self.GTM_AVCC_RN,
),
)
# Power/ground: VCCINT_GT_R, VCC_PMC, VCC_PSLP, GTM_AVCCAUX_L, GTM_AVCCAUX_RN, GTY_AVCCAUX_RS, GTY_AVCC_RS, RSVDGND, VCCAUX_PMC, VCC_IO
yield SymbolPartition(
left=(
*self.VCCINT_GT_R,
*self.VCC_PMC,
*self.VCC_PSLP,
*self.GTM_AVCCAUX_L,
),
right=(
*self.GTM_AVCCAUX_RN,
*self.GTY_AVCCAUX_RS,
*self.GTY_AVCC_RS,
*self.RSVDGND,
*self.VCCAUX_PMC,
*self.VCC_IO,
),
)
def __init__(self):
self.mappings = [
build_pad_mapping(self.landpattern, self.ball_assignments(), TOTAL_BALLS)
]
self.symbols = build_symbols(self.symbol_partitions())
# Ball coordinate tables for the rail lists, (row, col) sorted.
# fmt: off
_GND_BALLS: tuple[tuple[int, int], ...] = (
(0, 0), (0, 3), (0, 4), (0, 5), (0, 8), (0, 13), (0, 18),
(0, 23), (0, 26), (0, 27), (0, 28), (0, 29), (0, 30), (0, 31),
(0, 32), (0, 33), (0, 34), (0, 35), (0, 36), (1, 0), (1, 1),
(1, 2), (1, 5), (1, 6), (1, 7), (1, 8), (1, 10), (1, 15),
(1, 20), (1, 25), (1, 26), (1, 29), (1, 30), (1, 31), (1, 34),
(1, 35), (1, 36), (2, 0), (2, 3), (2, 4), (2, 5), (2, 8),
(2, 12), (2, 17), (2, 22), (2, 26), (2, 27), (2, 28), (2, 31),
(2, 32), (2, 33), (2, 36), (3, 0), (3, 1), (3, 2), (3, 5),
(3, 6), (3, 7), (3, 8), (3, 14), (3, 19), (3, 25), (3, 26),
(3, 27), (3, 28), (3, 29), (3, 30), (3, 31), (3, 34), (3, 35),
(3, 36), (4, 0), (4, 3), (4, 4), (4, 5), (4, 8), (4, 11),
(4, 16), (4, 21), (4, 25), (4, 28), (4, 31), (4, 32), (4, 33),
(4, 36), (5, 0), (5, 1), (5, 2), (5, 5), (5, 6), (5, 7),
(5, 8), (5, 13), (5, 18), (5, 23), (5, 25), (5, 26), (5, 27),
(5, 28), (5, 29), (5, 30), (5, 31), (5, 34), (5, 35), (5, 36),
(6, 0), (6, 3), (6, 4), (6, 5), (6, 8), (6, 9), (6, 10),
(6, 15), (6, 20), (6, 23), (6, 24), (6, 25), (6, 28), (6, 31),
(6, 32), (6, 33), (6, 36), (7, 0), (7, 1), (7, 2), (7, 3),
(7, 6), (7, 7), (7, 8), (7, 10), (7, 11), (7, 15), (7, 17),
(7, 19), (7, 21), (7, 23), (7, 26), (7, 27), (7, 28), (7, 29),
(7, 30), (7, 31), (7, 34), (7, 35), (7, 36), (8, 0), (8, 3),
(8, 4), (8, 5), (8, 6), (8, 9), (8, 11), (8, 12), (8, 14),
(8, 16), (8, 18), (8, 20), (8, 22), (8, 23), (8, 24), (8, 28),
(8, 31), (8, 32), (8, 33), (8, 36), (9, 0), (9, 1), (9, 2),
(9, 3), (9, 6), (9, 7), (9, 11), (9, 13), (9, 15), (9, 17),
(9, 19), (9, 21), (9, 23), (9, 26), (9, 28), (9, 29), (9, 30),
(9, 31), (9, 34), (9, 35), (9, 36), (10, 0), (10, 3), (10, 4),
(10, 5), (10, 6), (10, 9), (10, 11), (10, 12), (10, 14), (10, 16),
(10, 18), (10, 20), (10, 22), (10, 23), (10, 24), (10, 28), (10, 31),
(10, 32), (10, 33), (10, 36), (11, 0), (11, 1), (11, 2), (11, 3),
(11, 6), (11, 7), (11, 11), (11, 13), (11, 15), (11, 17), (11, 19),
(11, 21), (11, 23), (11, 26), (11, 28), (11, 29), (11, 30), (11, 33),
(11, 34), (11, 35), (11, 36), (12, 0), (12, 3), (12, 4), (12, 5),
(12, 6), (12, 8), (12, 9), (12, 11), (12, 12), (12, 14), (12, 16),
(12, 18), (12, 20), (12, 22), (12, 23), (12, 24), (12, 28), (12, 31),
(12, 32), (12, 33), (12, 36), (13, 0), (13, 1), (13, 2), (13, 3),
(13, 6), (13, 7), (13, 8), (13, 10), (13, 11), (13, 13), (13, 15),
(13, 17), (13, 19), (13, 21), (13, 23), (13, 24), (13, 25), (13, 26),
(13, 28), (13, 29), (13, 30), (13, 33), (13, 34), (13, 35), (13, 36),
(14, 0), (14, 3), (14, 4), (14, 5), (14, 8), (14, 9), (14, 11),
(14, 12), (14, 14), (14, 16), (14, 18), (14, 20), (14, 22), (14, 24),
(14, 28), (14, 31), (14, 32), (14, 33), (14, 36), (15, 0), (15, 1),
(15, 2), (15, 3), (15, 6), (15, 7), (15, 8), (15, 11), (15, 13),
(15, 15), (15, 17), (15, 19), (15, 21), (15, 23), (15, 24), (15, 25),
(15, 26), (15, 28), (15, 29), (15, 30), (15, 33), (15, 34), (15, 35),
(15, 36), (16, 0), (16, 3), (16, 4), (16, 5), (16, 8), (16, 9),
(16, 11), (16, 12), (16, 14), (16, 16), (16, 18), (16, 20), (16, 22),
(16, 24), (16, 28), (16, 31), (16, 32), (16, 33), (16, 36), (17, 0),
(17, 1), (17, 2), (17, 3), (17, 6), (17, 7), (17, 8), (17, 10),
(17, 11), (17, 13), (17, 17), (17, 19), (17, 21), (17, 23), (17, 24),
(17, 25), (17, 26), (17, 28), (17, 29), (17, 30), (17, 33), (17, 34),
(17, 35), (17, 36), (18, 0), (18, 1), (18, 2), (18, 3), (18, 4),
(18, 5), (18, 6), (18, 9), (18, 11), (18, 12), (18, 16), (18, 18),
(18, 20), (18, 22), (18, 24), (18, 28), (18, 31), (18, 32), (18, 33),
(18, 36), (19, 2), (19, 3), (19, 4), (19, 7), (19, 11), (19, 13),
(19, 17), (19, 19), (19, 21), (19, 23), (19, 24), (19, 25), (19, 26),
(19, 28), (19, 29), (19, 30), (19, 33), (19, 34), (19, 35), (19, 36),
(20, 0), (20, 1), (20, 4), (20, 5), (20, 9), (20, 11), (20, 12),
(20, 16), (20, 18), (20, 20), (20, 22), (20, 24), (20, 28), (20, 31),
(20, 32), (20, 33), (20, 36), (21, 2), (21, 3), (21, 4), (21, 7),
(21, 9), (21, 10), (21, 11), (21, 13), (21, 15), (21, 17), (21, 19),
(21, 21), (21, 23), (21, 24), (21, 25), (21, 26), (21, 28), (21, 29),
(21, 30), (21, 33), (21, 34), (21, 35), (21, 36), (22, 0), (22, 1),
(22, 4), (22, 5), (22, 7), (22, 8), (22, 9), (22, 11), (22, 14),
(22, 16), (22, 18), (22, 20), (22, 22), (22, 24), (22, 28), (22, 31),
(22, 32), (22, 33), (22, 36), (23, 0), (23, 1), (23, 2), (23, 3),
(23, 4), (23, 7), (23, 10), (23, 13), (23, 17), (23, 19), (23, 21),
(23, 23), (23, 24), (23, 25), (23, 26), (23, 28), (23, 29), (23, 30),
(23, 31), (23, 34), (23, 35), (23, 36), (24, 2), (24, 3), (24, 4),
(24, 5), (24, 6), (24, 7), (24, 9), (24, 12), (24, 15), (24, 16),
(24, 18), (24, 20), (24, 22), (24, 24), (24, 26), (24, 27), (24, 28),
(24, 31), (24, 32), (24, 33), (24, 36), (25, 0), (25, 1), (25, 4),
(25, 7), (25, 8), (25, 11), (25, 14), (25, 17), (25, 19), (25, 21),
(25, 23), (25, 25), (25, 27), (25, 28), (25, 29), (25, 30), (25, 31),
(25, 34), (25, 35), (25, 36), (26, 2), (26, 3), (26, 4), (26, 5),
(26, 6), (26, 7), (26, 10), (26, 12), (26, 14), (26, 16), (26, 18),
(26, 20), (26, 22), (26, 24), (26, 26), (26, 27), (26, 28), (26, 31),
(26, 32), (26, 33), (26, 36), (27, 0), (27, 1), (27, 4), (27, 6),
(27, 9), (27, 11), (27, 13), (27, 15), (27, 17), (27, 19), (27, 21),
(27, 23), (27, 25), (27, 27), (27, 28), (27, 29), (27, 30), (27, 31),
(27, 34), (27, 35), (27, 36), (28, 2), (28, 3), (28, 4), (28, 8),
(28, 10), (28, 12), (28, 14), (28, 16), (28, 18), (28, 20), (28, 22),
(28, 24), (28, 26), (28, 28), (28, 31), (28, 32), (28, 33), (28, 36),
(29, 0), (29, 1), (29, 4), (29, 7), (29, 10), (29, 13), (29, 16),
(29, 19), (29, 22), (29, 25), (29, 28), (29, 29), (29, 30), (29, 33),
(29, 34), (29, 35), (29, 36), (30, 2), (30, 3), (30, 4), (30, 6),
(30, 9), (30, 12), (30, 15), (30, 18), (30, 21), (30, 24), (30, 27),
(30, 28), (30, 31), (30, 32), (30, 33), (30, 36), (31, 0), (31, 1),
(31, 4), (31, 5), (31, 8), (31, 11), (31, 14), (31, 17), (31, 20),
(31, 23), (31, 26), (31, 28), (31, 29), (31, 30), (31, 33), (31, 34),
(31, 35), (31, 36), (32, 0), (32, 1), (32, 2), (32, 3), (32, 4),
(32, 7), (32, 12), (32, 17), (32, 22), (32, 27), (32, 30), (32, 31),
(32, 32), (32, 33), (32, 36), (33, 2), (33, 3), (33, 4), (33, 9),
(33, 14), (33, 19), (33, 24), (33, 29), (33, 33), (33, 34), (33, 35),
(33, 36), (34, 0), (34, 1), (34, 4), (34, 6), (34, 11), (34, 16),
(34, 21), (34, 26), (34, 31), (34, 36), (35, 2), (35, 3), (35, 4),
(35, 8), (35, 13), (35, 18), (35, 23), (35, 28), (35, 33), (36, 0),
(36, 1), (36, 4), (36, 5), (36, 10), (36, 15), (36, 20), (36, 25),
(36, 30), (36, 35), (36, 36),
)
# fmt: on
# fmt: off
_GTM_AVCCAUX_L_BALLS: tuple[tuple[int, int], ...] = (
(16, 25), (18, 25),
)
# fmt: on
# fmt: off
_GTM_AVCCAUX_RN_BALLS: tuple[tuple[int, int], ...] = (
(10, 10), (12, 10),
)
# fmt: on
# fmt: off
_GTM_AVCC_L_BALLS: tuple[tuple[int, int], ...] = (
(8, 25), (10, 25), (12, 25), (14, 25), (20, 25), (22, 25),
)
# fmt: on
# fmt: off
_GTM_AVCC_RN_BALLS: tuple[tuple[int, int], ...] = (
(8, 10), (13, 9), (14, 10),
)
# fmt: on
# fmt: off
_GTM_AVTT_L_BALLS: tuple[tuple[int, int], ...] = (
(9, 27), (11, 27), (13, 27), (15, 27), (17, 27), (19, 27), (21, 27),
(23, 27),
)
# fmt: on
# fmt: off
_GTM_AVTT_RN_BALLS: tuple[tuple[int, int], ...] = (
(7, 9), (9, 8), (11, 8), (12, 7),
)
# fmt: on
# fmt: off
_GTY_AVCCAUX_RS_BALLS: tuple[tuple[int, int], ...] = (
(17, 9), (18, 10),
)
# fmt: on
# fmt: off
_GTY_AVCC_RS_BALLS: tuple[tuple[int, int], ...] = (
(16, 10), (20, 10),
)
# fmt: on
# fmt: off
_GTY_AVTT_RS_BALLS: tuple[tuple[int, int], ...] = (
(19, 8), (20, 6), (21, 8), (22, 6),
)
# fmt: on
# fmt: off
_NC_BALLS: tuple[tuple[int, int], ...] = (
(0, 1), (0, 2), (0, 6), (0, 7), (1, 3), (1, 4), (2, 1),
(2, 2), (2, 6), (2, 7), (3, 3), (3, 4), (4, 1), (4, 2),
(4, 6), (4, 7), (5, 3), (5, 4), (6, 1), (6, 2), (6, 6),
(6, 7), (7, 4), (7, 5), (8, 1), (8, 2), (8, 7), (8, 8),
(9, 4), (9, 5), (9, 9), (9, 10), (10, 1), (10, 2), (10, 7),
(10, 8), (11, 4), (11, 5), (11, 9), (11, 10), (12, 1), (12, 2),
(13, 4), (13, 5), (14, 1), (14, 2), (14, 6), (14, 7), (15, 4),
(15, 5), (16, 1), (16, 2), (16, 6), (16, 7), (17, 4), (17, 5),
(18, 7), (18, 8), (19, 9), (19, 10),
)
# fmt: on
# fmt: off
_RSVDGND_BALLS: tuple[tuple[int, int], ...] = (
(20, 14), (20, 15),
)
# fmt: on
# fmt: off
_VCCAUX_BALLS: tuple[tuple[int, int], ...] = (
(15, 16), (15, 18), (15, 20), (24, 17), (24, 19), (24, 21),
)
# fmt: on
# fmt: off
_VCCAUX_PMC_BALLS: tuple[tuple[int, int], ...] = (
(22, 13), (23, 14),
)
# fmt: on
# fmt: off
_VCCINT_BALLS: tuple[tuple[int, int], ...] = (
(7, 14), (7, 16), (7, 18), (7, 20), (7, 22), (8, 13), (8, 15),
(8, 17), (8, 19), (8, 21), (9, 14), (9, 16), (9, 18), (9, 20),
(9, 22), (11, 14), (11, 16), (11, 18), (11, 20), (11, 22), (12, 13),
(12, 21), (13, 14), (13, 16), (13, 18), (13, 20), (13, 22), (14, 13),
(14, 15), (14, 17), (14, 19), (14, 21), (15, 12), (15, 14), (15, 22),
(16, 13), (16, 15), (16, 17), (16, 19), (16, 21), (17, 12), (17, 16),
(17, 18), (17, 20), (17, 22), (18, 13), (18, 17), (18, 19), (18, 21),
(19, 12), (19, 16), (19, 18), (19, 20), (19, 22), (20, 13), (20, 17),
(20, 19), (20, 21), (21, 12), (21, 14), (21, 16), (22, 17), (22, 19),
(22, 21), (23, 16), (23, 18), (23, 20), (23, 22), (24, 23), (24, 25),
(25, 16), (25, 18), (25, 20), (25, 22), (25, 24), (25, 26), (26, 11),
(26, 13), (26, 15), (26, 17), (26, 19), (26, 21), (26, 23), (26, 25),
)
# fmt: on
# fmt: off
_VCCINT_GT_L_BALLS: tuple[tuple[int, int], ...] = (
(14, 23), (16, 23), (18, 23), (20, 23), (22, 23),
)
# fmt: on
# fmt: off
_VCCINT_GT_R_BALLS: tuple[tuple[int, int], ...] = (
(9, 12), (11, 12), (13, 12),
)
# fmt: on
# fmt: off
_VCCO_500_BALLS: tuple[tuple[int, int], ...] = (
(24, 8), (25, 9),
)
# fmt: on
# fmt: off
_VCCO_501_BALLS: tuple[tuple[int, int], ...] = (
(27, 7), (27, 8),
)
# fmt: on
# fmt: off
_VCCO_502_BALLS: tuple[tuple[int, int], ...] = (
(23, 8), (23, 9),
)
# fmt: on
# fmt: off
_VCCO_503_BALLS: tuple[tuple[int, int], ...] = (
(26, 8), (26, 9),
)
# fmt: on
# fmt: off
_VCCO_700_BALLS: tuple[tuple[int, int], ...] = (
(31, 9), (32, 9), (32, 10),
)
# fmt: on
# fmt: off
_VCCO_701_BALLS: tuple[tuple[int, int], ...] = (
(31, 12), (31, 13), (32, 13),
)
# fmt: on
# fmt: off
_VCCO_702_BALLS: tuple[tuple[int, int], ...] = (
(31, 16), (32, 15), (32, 16),
)
# fmt: on
# fmt: off
_VCC_IO_BALLS: tuple[tuple[int, int], ...] = (
(28, 13), (28, 15),
)
# fmt: on
# fmt: off
_VCC_PMC_BALLS: tuple[tuple[int, int], ...] = (
(22, 12), (23, 11), (23, 12),
)
# fmt: on
# fmt: off
_VCC_PSFP_BALLS: tuple[tuple[int, int], ...] = (
(25, 10), (25, 12), (25, 13), (25, 15),
)
# fmt: on
# fmt: off
_VCC_PSLP_BALLS: tuple[tuple[int, int], ...] = (
(24, 11), (24, 13), (24, 14),
)
# fmt: on
# fmt: off
_VCC_RAM_BALLS: tuple[tuple[int, int], ...] = (
(12, 15), (12, 17), (12, 19), (21, 18), (21, 20), (21, 22),
)
# fmt: on
# fmt: off
_VCC_SOC_BALLS: tuple[tuple[int, int], ...] = (
(10, 13), (10, 15), (10, 17), (10, 19), (10, 21), (27, 10), (27, 12),
(27, 14), (27, 16), (27, 18), (27, 20), (27, 22), (27, 24), (27, 26),
(28, 17), (28, 19), (28, 21), (28, 23),
)
# fmt: on
Device: type[XCVP1002] = XCVP1002
