Net

net is a JITX statement that defines an electrical connection between ports of components and modules. The net statement is only valid inside pcb-module contexts. With the net statement we can connect single pins, bundles, and port arrays, as long as the types match. Optionally, nets can be assigned names.

Signature

The net statement has two basic forms:

Forward Declaration - This form is used to declare a net by name before using it in a circuit.
Instantiation - This form is used to cosntruct a net or add ports to an existing net directly in a given statement.

; Forward Declaration
net <NAME>
net <NAME> : <TYPE>

; Instantiation
net (<REF-1>, <REF-2>, ...)
net <NAME> (<REF-1>, <REF-2>, ...)
net <NAME> : <TYPE> (<REF-1>, <REF-2>, ...)

<NAME> - Symbol name for this net that is unique in the current module context. This <NAME> parameter is optional in the instantiation form. If not present, then this is considered an anonymous net.
<TYPE> - An optional port type that allows the construction of arbitrary net port types. Typically this type would be a pcb-bundle type
(<REF-1>, ...) - The list of refs provides the identification of which pins or other nets to form connections with in the instantiation form.

Public Accessibility

By default, all net statements are private. This means that the connection created by the net statement is not accessible from outside the pcb-module context what it was written. A public prefix modifier can be added to a named net statement to allow access by external entities.

Example

pcb-module transceiver:
  ...
  public net OSC (mixer.osc-in, crystal.p[1])

pcb-module top-level:

  inst U1 : transceiver
  inst debug : connector

  net (U1.OSC, debug.p[1])

In this example the net OSC in the transceiver module is marked public which means it is accessible from the parent context top-level. If OSC had not been marked public, then the JITX runtime would have issued a Cannot access named field 'U1.OSC'. error.

Usage

Single Pin Nets

pcb-module v-div:
  port vin
  port vout
  port gnd

  inst R1 : chip-resistor(10.0e3)
  inst R2 : chip-resistor(10.0e3)

  ; Anonymous Net Construction
  net (vin,     R1.p[1])
  net (R1.p[2], R2.p[1], vout)
  net (R2.p[2], gnd)

This is the most common usage pattern for net statements in a circuit. All of the nets are anonymous (ie, they have no specific given name). These nets will each be assigned a name by the JITX runtime as the circuit design is elaborated.

Named `net` in `net`

We can use named nets as an element of the reference list in a subsequent net statement.

pcb-module multiple-sensors:
  ; Forward Declaration of the Ground Net
  net GND

  inst U1 : Accelerometer
  net (U1.gnd, GND)

  inst U2 : Temperature-Sensor
  ; This is legal
  net OTHER-NAME (U2.gnd, GND)

In this example, we forward declare the GND net for our circuit so that we can use it connect the ground connection of our various sensor components.

Notice that you can create additional net reference names (ie, OTHER-NAME in this example) that are aliases to the GND net.

Net on Bundles / Arrays

The net statement also works on Bundle and PortArray types.

pcb-bundle SPI:
  pin poci
  pin pico
  pin sclk

pcb-component sd-card:
  port bus : SPI
  ...

pcb-component mcu:
  port bus : SPI
  ...

pcb-module top-level: 

  inst host : mcu
  inst dev : sd-card

  net (host.bus, dev.bus)

In this example, the two components host and dev both export ports of type SPI. The net statement in this case constructs 3 distinct connections:

host.bus.poci <=> dev.bus.poci
host.bus.pico <=> dev.bus.pico
host.bus.sclk <=> dev.bus.sclk

Attempting to net two ports of different types (ie, a pin to a bundle, or an i2c bundle to an SPI bundle) will result in an error.

PortArray types behave similarly where a net statement makes an element-wise 1:1 connection between the pins of the PortArray ref instances.

Arrays of Nets

With forward declaration, we can construct arrays of nets for usage in a for loop or other sequence:


pcb-bundle MIPI-CSI:
  port clk : diff-pair
  port data : diff-pair

pcb-module my-module: 

  val num-cams = 16

  inst host : mcu
  inst cams : camera[ num-cams ]

  net bus:MIPI-CSI[ num-cams ]

  for i in 0 to num-cams do:
    net (bus[i], host.MIPI[i], cams[i].MIPI)

In this example, we forward declare an array of MIPI busses. We then use a for loop to make num-cams connections between the host and the each camera.

In this example we could have skipped the forward declaration of the net and used the following and accomplished the same connections:

net (host.MIPI[i], cams[i].MIPI)

The short comings of this approach are:

If we wanted to set a name for these nets, then this becomes difficult
1. First, We would need to construct a string name for the net
  1. Example: val name = to-string("bus-%_" % [i])
2. Then we would need to apply this name some how to the net construction.
  1. The easiest way right now is to use the make-net function
  2. make-net(name, [host.MIPI[i], cams[i].MIPI])
Unless we somehow save the string name that we constructed above, then there is really no way to reference that net at a later time.

By forward declaring the net, we avoid these difficulties.

JITX Documentation