Source code for jitxexamples.essentials.signal_integrity

import jitx
from jitx.net import Topology
from jitx.sample import SampleDesign
from jitx.si import Constrain
from jitxlib.parts.query_api import Resistor, ResistorQuery



[docs]
class TopLevel(jitx.Circuit):
    A = Resistor(resistance=10.0)
    B = Resistor(resistance=10.0)
    C = Resistor(resistance=10.0)

    topos = [
        A.p1 >> B.p1 >> C.p1,
    ]

    def __init__(self):
        rs = jitx.current.substrate.routing_structure(50.0)
        self.cst = Constrain(Topology(self.A.p1, self.C.p1)).structure(rs)




[docs]
class signal_integrity_tests(SampleDesign):
    rquery = ResistorQuery(case="1206")
    circuit = TopLevel()